1. ASIC Development for Vertex Detector ’07 6/14 Y. Takubo (Tohoku university)

2. Introduction Motivation to develop readout ASIC A large number of FPCCD channel must be read with ASIC. Test sample will be delivered within 2007. Readout ASIC is necessary to test the FPCCD test sample. Today’s talk Requirement to the readout ASIC Chip design Schedule

3. ILC-FPCCD Pixel size : 5  m Thickness : 15  m Signal level : ~500e for penetration with large angle → Readout ASIC must be low noise. Wafer size  L1, L2 : 10 x 65 mm 2  L3-L6 : 20 x 100 mm 2 Readout channel : 16 or 32 ch  L1, L2 : 13,000 x 128 pix/ch  L3-L6 : 20,000 x 128 pix/ch ILC vertex detector is constructed with FPCCD wafers.

4. FPCCD vertex detector Size (mm 2 )ch/wafer# of wafers# of ch L1, L210 x 6516 15  x 2(z) 480 L3, L420 x10032 16  x 2(z) 1024 L5, L620 x 10032 24  x 2(z) 1536 Total2206080 cos  = 0.95 cos  = 0.9 L1 L6 FPCCD vertex detector # of wafers : 220 Readout channel : ~6000ch All pixels in one channel is read within 200ms Required power consumption : < 100W.  to be investigated Structure and performance of FPCCD determines requirement to the readout ASIC.

5. Requirement to the readout ASIC Amplifier, LPF, CDS, ADC and DSP are mounted on one chip. Readout rate : >10 Mpix/sec  [20000 x 128 pix]/[0.2 s] Total noise level including the CCD : <50 electrons Power consumption : < 10mW/ch (~100W/6000ch) Channel width : 0.64 mm  5  m x 128pix To achieve these requirement, readout ASIC is designed by Ikeda-san.

6. Block diagram of readout ASIC Design concept was made by Ikeda-san. From CCD Voltage amplifier Low-pass filter Charge-sharing ADC (6bit) LVDS driver Reset Gain control Band-width control Track/Hold Conversion CK(100MHz) Serial output 2 ADCs are activated alternatively. Specification of the ASIC design is summarized.

7. Specification of readout ASIC 0.35  m process by TSMC Size : 3 x 3 mm 2 # of pad : 80 # of signal channels : 4 AD conversion rate : 10 MHz x 2 Clock frequency : 100 MHz Data width : 6bit + sign bit Power rail : ±1.65 V Analog gain : adjustable Frequency bandwidth : adjustable Interface : LVDS/LVTTL Performance of the readout ASIC is estimated.

8. Expected performance Power consumption < 5 mW  Charge-sharing ADC realizes low power and fast AD conversion. Readout rate : 20 Mpix/sec  Data conversion rate : 10x2 MHz  130 ms/ch : [20000 x 128 pix/ch] x [5 x 10 － 8 s/pix] Channel width : 0.75mm (=3/4) To be evaluated Determination of signal scale Estimation of noise level

9. Schedule ~ August in 2007  Simulation study  Determination of chip design  Ordering the readout chip ~ January in 2008  The chip will be delivered.  Response test of the readout chip  Readout test of FPCCD with readout ASIC  Improvement of the chip design for the 2 nd prototype.

11. 2016/3/12Conceptual Design for FPCCD ASIC11 C1 C2 Gain= -C1/C2 To be arrange as a binary weighted array Located to improve peaking characteristics Switch for DC restoration Low noise amplification element Bias voltage generator To mitigate the clock-feedthru Source follower for DC level-shift Voltage amplifier

12. 2016/3/12Conceptual Design for FPCCD ASIC12 To subtract DC level during rest phase (CDS) Second-order low—pass filter with gm-C filter technique Band-pass node Low-pass node G=1 Low-pass filter

13. 2016/3/12Conceptual Design for FPCCD ASIC13 INPUT Parallel out Serial out Data valid Reference voltage Shift register Switch control and bit-storage For settleing OUTP OUTM Charge sharing successive approximation AD converter

14. 2016/3/12Conceptual Design for FPCCD ASIC14 MSBLSB 0.4 pF + 0.4 pF0.0625 pF Capacitor bank

15. 2016/3/12Conceptual Design for FPCCD ASIC15 Driven by clock Low-asserted for meta-stable transients Comparator

16. 2016/3/12Conceptual Design for FPCCD ASIC16 Driver Reciever LVDS interface

17. 2016/3/12Conceptual Design for FPCCD ASIC17 Driver Receiver LVTTL interface