1. A 12 bit 50 MS/s Dual Channel Time Domain Two Step ADC
Tibi Galambos, Vladimir Koifman, Anatoli Mordakhay
Analog Value Ltd.
May 13, 2019

2. Overview ADC Architecture Sampling Voltage to Time Converter
Sampling Latch Circuit
ADC Layout
Conclusions

3. ADC Architecture – Block Diagram

4. ADC Architecture – Algorithm
Fine bits – phase difference
Coarse bits – counters
Metastability avoidance
Counter decrement

5. Sampling Voltage to Time Converter - Schematics
Input voltage sampled on C1
C2 generates a constant shift to help using the full dynamic range
M1 acts as common source amplifier
M2 acts as pre-charged comparator
Idis is a switch-cap current source (see next slide)

6. Sampling Voltage to Time Converter – Current Source
The implementation uses the high frequency clocks from the PLL
Given the use of the same type of capacitors for the current source and the integrating capacitor, ADC gain is process independent and only sensitive to matching

7. Sampling Voltage to Time Converter - Waveforms
Input voltage sampled during F1
Linear Ramp and V2T conversion is done during F2

8. Sampling Latch - Schematics
M13 – distributed voltage source
M1, M2 measure the input voltage
When comp_p is low, the regenerative feedback circuit is pre-charged
On falling edge of comp_n the information is applied to the regenerative feedback (M9-M12)

9. ADC Test Chip and Layout

10. Conclusion
A novel 12 bit ADC was designed and fabricated in GF 22nm FDSOI technology
Power consumption (for 2 channels) is 4 mW
Silicon area 0.05 mm2
Measured an ENOB of 10.5

11. Thanks for your attention