EE121 John Wakerly Lecture #9 Sequential PLD timing ABEL sequential features Registers Counters Shift registers

Sequential PLD timing parameters

Registered outputs in ABEL “istype ’reg’;” for registered outputs “.CLK” suffix to specify clock-input signal “.OE” suffix to specify output-enable signal “:=” in assignment statements

Example (We’ll discuss state machines next time.) Inputs Combinational outputs Registered outputs (We’ll discuss state machines next time.) (We’ll discuss ABEL “state diagrams” later.

Example (cont’d.) Don’t forget!! (Foundation won’t tell you)

More complex registered outputs Additional suffixes used for more features Not needed in this class

Multibit registers and latches 74x175

8-bit (octal) register 74x374 3-state output

Other octal registers 74x273 asynchronous clear 74x377 clock enable

Octal latch 74x373 Register vs. latch, what’s the difference? Output enable Latch-enable input “C” or “G” Register vs. latch, what’s the difference? Register: edge-triggered behavior Latch: output follows input when G is asserted

ABEL code for octal register module Eight_Bit_Reg title '8-bit Edge-Triggered Register' Z74X374 device 'P16V8R'; " Input pins CLK, OE_L pin 1, 11; D1..D8 pin 2..9; " Output pins Q1..Q8 pin 19..12; " Set definitions D = [D1..D8]; Q = [Q1..Q8]; equations Q.CLK = CLK; Q := D; end Eight_Bit_Reg

Adding features is easy Clock enable + Synchronous clear + Asynchronous clear (only if PAL supports asynchronous reset) when CE then Q := D; else Q := Q; when SCLR then Q := 0; else when CE then Q := D; else Q := Q; Q.AR = ACLR;

Counters Any sequential circuit whose state diagram is a single cycle. RESET

LSB Synchronous counter Serial enable logic MSB

LSB Synchronous counter Parallel enable logic MSB

74x163 MSI 4-bit counter

74x163 internal logic diagram XOR gates embody the “T” function Mux-like structure for loading

Counter operation Free-running 16 Count if ENP and ENT both asserted. Load if LD is asserted (overrides counting). Clear if CLR is asserted (overrides loading and counting). All operations take place on rising CLK edge. RCO is asserted if ENT is asserted and Count = 15.

Free-running 4-bit ’163 counter “divide-by-16” counter

Modified counting sequence Load 0101 (5) after Count = 15 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5, 6, … “divide-by-11” counter

Another way Clear after Count = 1010 (10) trick to save gate inputs Clear after Count = 1010 (10) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2, 3, … “modulo-11” or “divide-by-11” counter

Counting from 3 to 12

Cascading counters RCO (ripple carry out) is asserted in state 15, if ENT is asserted.

Decoding binary-counter states

Decoder waveforms Glitches may or may not be a concern.

Glitch-free outputs Registered outputs delayed by one clock tick. We’ll show another way to get the same outputs later, using a shift register.

Counters in ABEL note reg vs. com don’t forget clock! reg com module Z74X163 title '4-bit Binary Counter' " Input and output pins CLK, LD_L, CLR_L, ENP, ENT pin; A, B, C, D pin; QA, QB, QC, QD pin istype 'reg'; RCO pin istype 'com'; " Active-level conversions CLR = !CLR_L; LD = !LD_L; " Set definitions INPUT = [D, C, B, A]; COUNT = [QD, QC, QB, QA]; Counters in ABEL note reg vs. com equations COUNT.CLK = CLK; COUNT := !CLR & ( LD & INPUT # !LD & (ENT & ENP) & (COUNT + 1) # !LD & !(ENT & ENP) & COUNT); RCO = (COUNT == [1,1,1,1]) & ENT; end Z74X163 don’t forget clock! reg com

Minimized sum-of-products equations QA := (CLR_L & LD_L & ENT & ENP & !QA # CLR_L & LD_L & !ENP & QA # CLR_L & LD_L & !ENT & QA # CLR_L & !LD_L & A); QB := (CLR_L & LD_L & ENT & ENP & !QB & QA # CLR_L & LD_L & QB & !QA # CLR_L & LD_L & !ENP & QB # CLR_L & LD_L & !ENT & QB # CLR_L & !LD_L & B); QC := (CLR_L & LD_L & ENT & ENP & !QC & QB & QA # CLR_L & LD_L & QC & !QA # CLR_L & LD_L & QC & !QB # CLR_L & LD_L & !ENP & QC # CLR_L & LD_L & !ENT & QC # CLR_L & !LD_L & C); QD := (CLR_L & LD_L & ENT & ENP & !QD & QC & QB & QA # CLR_L & !LD_L & D # CLR_L & LD_L & QD & !QB # CLR_L & LD_L & QD & !QC # CLR_L & LD_L & !ENP & QD # CLR_L & LD_L & !ENT & QD # CLR_L & LD_L & QD & !QA); RCO = (ENT & QD & QC & QB & QA); Minimized sum-of-products equations

Shift registers For handling serial data, such as RS-232 and modem transmission and reception, Ethernet links, SONET, etc. Serial-in, serial-out

Serial-to-parallel conversion Use a serial-in, parallel-out shift register

Parallel-to-serial conversion Use parallel-in, serial-out shift register mux

Do both Parallel-in, parallel-out shift register

“Universal” shift register 74x194 Shift left Shift right Load Hold

One stage of ’194

Serial data systems (e.g., TPC) Read discussion and study circuits in text.

Shift-register counters Ring counter

Johnson counter “Twisted ring” counter

LFSR counters Pseudo-random number generator 2n - 1 states before repeating Same circuits used in CRC error checking in Ethernet networks, etc.

Feedback equations for all values of n

Next time Read about shift registers in ABEL Sequential-circuit analysis and synthesis