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14 Digital Systems.

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Presentation on theme: "14 Digital Systems."— Presentation transcript:

1 14 Digital Systems

2 Figure 14.1 RS flip-flop symbol and truth table
Outputs Inputs S R Q 1 Present state Reset Set Disallowed

3 Figure 14.2 Timing diagram for the RS flip-flop
1 S R Q Time Flip-flop is reset is set (but = 0) already

4 Figure 14.3 Logic gate implementation of the RS flip-flop
Q R S

5 Figure 14.4 RS flip-flop with enable, present, and clear lines
Preset Enable Clear Q S R Timing diagram Q S R E Preset ( P ) Clear ( C

6 Figure 14.5 Data latch and associated timing diagram
Enable D Q E R S

7 Figure 14.6 D flip-flop functional diagram, symbol, and timing waveforms
Q 1 = 2 CLK Timing diagram Device symbol S E Functional diagram R

8 Figure 14.7 JK flip-flop functional diagram and device symbol
Q J K S 1 Functional diagram E 2 R Master Slave CLK

9 Figure 14.8 Truth table for JK flip-flop
n CLK Q JK flip-flop K +1 0 (reset) 1 (set) (toggle) 1

10 Functional representation
Figure Binary up counter functional representation, state table, and timing waveforms 3-bit binary counter Functional representation of binary counter Timing table State Input pulses Reset Clock input b 2 1 3 4 5 6 7 t Timing diagram

11 Figure 14.11 Decade counter Input pulses b 1 2 4-bit 3 Clock binary 4
1 2 3 4 5 6 7 8 9 10 b Input pulses Reset 4-bit binary counter

12 Figure Ripple counter Clock input 1 Input Q 3 2 J CLK K 1 1 1

13 Figure 14.15 Three-bit synchronous counter
Q Clock input 2 CLK

14 Figure Ring counter Init Q 3 S R CLK PR 1 2 CLR Clock input

15 Figure 14.21 Four-bit parallel register
Q b “Load” input 1 2 3 D CLK

16 Figure 14.22 Four-bit shift register
Q 3 2 D Serial output input Clock CLK

17 Figure 14.24 a b c d e f g C B A BCD to seven-segment decoder D

18 Figure 14.26 Three-bit binary counter and state diagram
3 Q 2 CLK 1 001 010 011 111 110 101 100 000

19 Figure 14.27 State diagram of a modulo-4 up-down counter
00 01 10 11

20 Figure 14.28 Karnaugh maps for flip-flop inputs in modulo-4 counter
d x Q 2 S R

21 Figure 14.29 Implementation of modulo-4 counter
S 1 Q R 2 x

22 Figure 14.30 Structure of a digital data acquisition and control system
User Sensor signals To displays actuators Signal interface Software Communication links Other computers and instrumentation systems Microcomputer


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