1. 1 Digital Design: Sequential Logic Blocks Credits : Slides adapted from: J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006 C.H. Roth, Fundamentals of Logic Design, 5/e, Thomson, 2004 R.H. Katz, G. Borriello, Contemporary Logic Design, 2/e, Prentice-Hall, 2005

2. 2 Registers A collection of 2 or more D flip flops with a common clock Registers are often used to store a collection of related bits (e.g. a byte of data in a computer) OUT4 Clr DQDQDQDQ OUT1OUT2OUT3 CLK IN1IN2IN3IN4 Clr Clear

3. 3 A “standard” 4-bit register IC

4. 4 A “standard” 8-bit register IC

5. 5 Registers with 3-state outputs (a) Symbol(b) Functional Diagram

6. 6 A “standard” 8-bit register with 3- state outputs

7. 7 Registers with clock enable 8 8 Q DCE LoadClkIn Out ClrClrN (a) Symbol D Q CK 0101 D Q CK 0101 D Q CK 0101 In0 CE ClrN In7 Clk In1 Out0 Out1 Out7

8. 8 A standard 8 bit register with clock enable (= “gated” clock)

9. 9 Registers application: Data Transfers

10. 10 Shift Registers It is a register that stores input values in sequence. At each clock tick the values stored are shifted from one flip flop to the adjacent block diagram

11. 11 Cascading Flip Flops t FF1 < T clock – T su2 + t skew Setup Constraint: t FF1 > T h2 + t skew Hold Constraint: If flip flops were ideal (t FF = 0) shift registers would not work ! The hold time constraint would not be satisfied !! For long shift registers, skew can easily become an issue and cause hold time constraint to be violated

12. 12 Shift Registers (cont’d)

13. 13 Shift Registers (cont’d)

14. 14 Shift registers (cont’d)

15. 15 clear sets the register contents and output to 0 s1 and s0 determine the shift function s0s1function 00hold state 01shift right 10shift left 11load new input left_in left_out right_out right_in Universal shift register serial or parallel inputs serial or parallel outputs permits shift left or right shift in new values from left or right clear output input s0 s1 clock Universal Shift Register

16. 16 parallel inputs parallel outputs serial transmission Shift register application Parallel-to-serial conversion for serial transmission Serial-to-parallel conversion Parallel-to-serial conversion

17. 17 CLK Shift register application (cont’d) Pattern Recognizer in this case, recognizing the pattern 1001

18. 18 Ring Counter counters are systems that sequences through a fixed set of patterns in this case the sequence is 1000, 0100, 0010, 0001 provided that one of the given patterns is forced as initial state (by loading or set/reset) Shift register application (cont’d) DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK START SRRR NOTE: with 4 FF we make only 4 patterns

19. 19 Johnson (= Moebius = Twisted-ring) Counter Shift register application (cont’d) DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK How does this counter work?  Counts through the sequence: 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 NOTE: with 4 FF we make 8 patterns. Adjacent patterns have distance one (glitch free decoding) we can use 0000 or 1111 as reset state

20. 20 Ring and Johnson counter Timings

21. 21 Binary Counters A counter is a clocked sequential circuit that sequences through a fixed set of patterns A counter with m-states is called a modulo-m-counter, or sometimes a divide-by-m counter The most commonly used counter type is an n-bit binary counter (each of the states is encoded as the corresponding n-bit binary integer)

22. 22 Binary Counters (cont’d) Ripple counters Don’t use them !!! The output of the flip-flops are fed into the clock pin causing skew. As a result reliability becomes an issue (especially for high speed applications). Synchronous counters The operation of the flip flops is synchronized by a common clock.

23. 23 Synchronous Binary Counters

24. 24 Synchronous Binary Counters (cont’d)

25. 25 Sync. Binary Counters with T-FF Q A toggles always (every clock tick) Q B toggles every time Q A = 1 Q C toggles every time Q A AND Q B are both 1

26. 26 Sync. Binary Counters with D-FF XOR decides when bit should be toggled The toggling rule is as follows: always for low-order bit; only when first bit is true for second bit; only when first and second bit are true for third bit; and so on

27. 27 Example: Binary Up/Down Counter

28. 28 Binary Up/Down Counter (cont’d)