 # Counters.

## Presentation on theme: "Counters."— Presentation transcript:

Counters

Counters Counters are sequential circuits which "count” through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage: Ripple counters (Asynchronous counter) Synchronous counter

Ripple Counters – Clock is connected to the flip-flop clock input on the LSB bit flip-flop – For all other bits, a flip-flop output is connected to the clock input, thus circuit is not truly synchronous – Output change is delayed more for each bit toward the MSB. – Resurgent because of low power consumption

Synchronous Counters – Clock is directly connected to the flip-flop clock inputs – Logic is used to implement the desired state sequencing

Revision of Ripple Counters
Let’s look at some slides from Digit 1.

A 2-bit asynchronous (ripple) binary counter (Rev)
Both flip-flops are assumed to be initially RESET (Q low) Q0 is always the LSB unless otherwise specified

The Timing diagram for 2 bit Asynchronous Binary Counter (Rev)
This is a complete timing diagram & propagation delay time are not indicated. Overall timing diagram they are normally omitted for simplicity but it is very important in design & troubleshooting purposes

The Binary State Sequence for 2 bit Asynchronous Binary Counter (Rev)
CLOCK PULSE Q1 Q0 Initially 1 2 3 4 (recycles)

3-bit asynchronous binary counter and its timing diagram for one cycle
3-bit asynchronous binary counter and its timing diagram for one cycle. (Rev)

Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter (Rev)

The Binary State Sequence for a 3-bit Binary Counter (Rev)
CLOCK PULSE Q2 Q1 Q0 Initially 1 2 3 4 5 6 7 8 (recycles)

Four-bit asynchronous binary counter and its timing diagram (Rev)

The 74LS93A 4-bit asynchronous binary counter logic diagram
The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)

Ripple Counter How does it works?
– When there is a positive Clock edge on the clock input of A, A complements – The clock input for flip flop B is the Complemented output of flip-flop A – When flip A changes from 1 to 0, there is a positive edge on the clock input of B causing B to complement

Ripple Counter

Ripple Counter

Ripple Counter • The arrows show the cause-effect relationship
• The corresponding sequence of states => (B,A) = (0,0),(0,1), (1,0), (1,1), (0,0), (0,1), … • Each additional bit, C, D, …behaves like bit B, changing half as frequently as the bit before it. • For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0), …

Ripple Counter

Ripple Counter • These circuits are called ripple counters because each edge sensitive transition (positive in the example) causes a change in the next flip-flop’s state. • The changes “ripple” upward through the chain of flip-flops, i. e., each transition occurs after a clock-to-output delay from the stage before. • To see this effect in detail look at the waveforms on the next slide.

Ripple Counter

Ripple Counter • Starting with C = B = A = 1, equivalent to (C,B,A) = 7 base 10, the next clock increments the count to (C,B,A) = 0 base 10. In fine timing detail: – The clock to output delay tPHL causes an increasing delay from clock edge for A each stage transition. – Thus, the count “ripples” from least to most B significant bit. – For n bits, total worst case C delay is n tPHL.

Revision of synchronous counter
Slides from Digit 1

SYNCHRONOUS COUNTERS (Rev)
All the flip-flops in the counter are clocked at the same time by a common clock pulse (external clock) 2 advantages compared to Asynchronous Counter : 1) Very less propagation delay time 2) Able to perform counting in random mode (eg : 0,1,3,5,8, …,0,1,3,5,8,..)

A 2-bit synchronous binary counter (Rev)
Assumed initial in binary 0 states meaning that both flip--flops are in RESET condition.

Timing diagram for 2-bit synchronous counter (Rev)

A 3-bit synchronous binary counter (Rev)

Timing diagram for the counter (Rev)

Synchronous Counter • To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. • For an up-counter, use an incrementer

Synchronous Counter

Synchronous Counter • Internal Logic • Count Enable • Carry Out
XOR complements each bit AND chain causes complement of a bit if all bits toward LSB from it equal 1 • Count Enable Forces all outputs of AND chain to 0 to “hold” the state • Carry Out Added as part of incrementer Connect to Count Enable of additional 4-bit counters to form larger counters

Synchronous Counter

The 74HC163 4-bit synchronous binary counter
The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

Timing example for a 74HC163.

The 74LS160 synchronous BCD decade counter
The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)

Timing example for a 74LS160.

Other Counters – Down Counter - counts downward instead of upward
– Up-Down Counter - counts up or down depending on value a control input such as Up/Down – Parallel Load Counter - Has parallel load of values available depending on control input such as Load • Divide-by-n (Modulo n) Counter – Count is remainder of division by n which n may not be a power of 2 or – Count is arbitrary sequence of n states specifically designed state-by-state – Includes modulo 10 which is the BCD counter

A basic 3-bit up/down synchronous counter (Rev)

Up/Down Synchronous Counter (Rev)
Up Synchronous Counter : UP is set to ‘1’ and AND gate 1 is active causing output OR gate 1 is HIGH. This will cause Q1 output toggling. The AND gate 2 also active causes Q2 toggling Because of JK connection from Q output, the counting sequence is UP. Down Synchronous Counter : DOWN is set to ‘1’ and AND gate 3 is active causing output OR gate 1 is HIGH. This will cause Q1 output toggling. The AND gate 4 also active causes Q2 toggling Because of JK connection from Q output, the counting sequence is UP

Timing Diagram Up/Down Synchronous Counter (Rev)

The 74HC190 up/down synchronous decade counter.

Timing example for a 74HC190.

Add path for input data enabled for Load = 1 Add logic to : Disable count logic for Load = 1 Disable feedback from outputs for Load = 1 Enable count logic for Load = 0 & Count = 1

The resulting function table : Load Count Action Hold Stored Value 1 Count Up Stored Value X Load D

Converting parallel load counter into sync. BCD counter
Connect an external AND gate to LOAD Start with all-zero output (0000) COUNT input always HIGH (1) BCD counts from 0000 to 1001 To ensure LOAD = 1, Q0 and Q3 must be HIGH LOAD input (D0  D3) = 0000

Converting parallel load counter into sync. BCD counter

Synchronous BCD Counter
Present State Next State Q8 Q4 Q2 Q1 D8 D4 D2 D1 1 .. Using D – type FF, list the present and next states in this Table.

Synchronous BCD Counter
Y = 1, when present state = 1001 FF input equations Obtained from next – state values Simplify using K – map 1010  1111 (don’t care) Y = Q1Q8

Counting Modulo N A counter that goes through a repeated sequence of N states Maximum decimal number to be counted : If Mod 16, then the max decimal number is 15 If Mod N = 2n then the max decimal counted is N-1 To determine the required number of flip-flops: n flip-flop 2n output = Mod N

Counting Modulo 7 Use a synchronous 4 – bit binary counter with a synchronous load and clear LOAD – detect count “6” and load “0” Gives count of ( 0,1,2,3,4,5,6,0,1….) Using don’t care for states above 0110, detect number “6” when LOAD = Q2.Q1

Counting Modulo 7

Counting Modulo 6 : special requirement
Requirement : synchronously preset “9” on RESET and LOAD “9” on terminal count “14” Use a synchronous, 4 – bit counter with a synchronous LOAD Use LOAD signal to : preset count to “9” detect count “14” Give count of (9,10,11,12,13,14,9,10,…)

Counting Modulo 6 : special requirement

Arbitrary Count Sequence
Design a counter with six states as in table below

Arbitrary Count Sequence
2 states are not included : 011 and 111 Simplified equations :

Arbitrary Count Sequence
Logic diagram of the counter

CASCADE COUNTERS Two cascaded counters (all J and K inputs are HIGH).

Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs.

Example: Determine the overall modulus of the two cascaded counter for (a) and (b)
For (a) the overall modulus for the 3 counter configuration is 8 x 12 x 16 = 1536 for (b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x 5 = 1400

A divide-by-100 counter using two 74LS160 decade counters.

A divide-by-40,000 counter using 74HC161 4-bit binary counters
A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in each counter).

Decoding of state 6 (110). COUNTER DECODING
* To determine when the counter is in a certain states in its sequence by using decoders or logic gates. Decoding of state 6 (110).

A 3-bit counter with active-HIGH decoding of count 2 and count 7.

A basic decade (BCD) counter and decoder.

Outputs with glitches from the previous decoder
Outputs with glitches from the previous decoder. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

The basic decade counter and decoder with strobing to eliminate glitches.

Strobed decoder outputs for the circuit

Simplified logic diagram for a 12-hour digital clock.

Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

Logic diagram for hours counter and decoders
Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.

Functional block diagram for parking garage control.

Logic diagram for modulus-100 up/down counter for automobile parking control.

Parallel-to-serial data conversion logic.

Example of parallel-to-serial conversion timing for the previous circuit

Thank You.