VHDL Mealy and Moore model 순차논리회로 (FSM) 의 종류 - Mealy 순차회로 : 회로의 출력이 현재상태와 현재입력에 의해 결정 Next State Logic (combinational) Current state Register (sequential) Inputs Outputs Current State Output Asynchronous reset

VHDL Mealy and Moore model Y=(A+B)x′ , A(t+1)=Ax + Bx, B(t+1)=A′x

VHDL Mealy and Moore model 순차논리회로 (FSM) 의 종류 - Moore 순차회로 : 회로의 출력이 현재상태에 의해서만 결정 Current State Next State Logic (combinational) Current state Register (sequential) Next State Inputs Asynchronous reset Output Logic (combinational) Outputs

VHDL Mealy and Moore model Y=AB, TA=Bx, TB=x

VHDL Mealy and Moore model 다음의 회로는 Mealy 인가 Moore 인가? (1) Input Reg. Logic input output (3) Logic Output Reg. input clock output (2) clock

VHDL Mealy and Moore model FSM 을 위한 VHDL 기술은 두 부분으로 나누어 진다. 1. A Combinatorial part – input signal이 바뀔 때 마다 동작한다. (Sensitivity list - input signals, state) comb : process (input_signals, state) ... if (input = ”01”) then a.output:= ..... a.next_state:= .... 2. A sequential part – Clock 이 바뀔 때 마다 동작한다. (Sensityivity list - only clock or clock, reset) seq : process(clk) If (clk’event) and (clk = ’1’) then... VHDL 구문

Current state Register (sequential) VHDL Mealy and Moore model Next State Logic (combinational) Current state Register (sequential) Inputs Outputs Current State Output 2개 (blue and red) 혹은 3개의 Process (red) 문으로 회로를 표현 가능

VHDL Mealy and Moore model FSM 을 위한 VHDL 기술 방법. - Process 문을 이용하여 Logic 및 Register의 동작을 표시 - State의 데이터 type는 열거형 (enumeration type) 사용 - 초기상태를 반드시 규정: reset conditions - next state로 의 전이(transition)은 case 문사용 - 입력 조건은 if~else 을 사용 모든 조건에 대하여 상태 출력을 할당 feedback 엔 signal 과 변수 모두 사용 가능

VHDL Mealy and Moore model Sequential description ARCHITECTURE behave OF d_register IS BEGIN PROCESS(clk) IF clk’EVENT AND (clk=‘1’) THEN q<=D; END IF; END PROCESS; END behave;

VHDL Mealy and Moore model CLK 의 표현 방법 1. IF 문을 이용한 CLK 의 표현 if SIGNAL’event and SIGNAL = ’1’ -- rising edge if NOT SIGNAL’stable and SIGNAL = ’1’ -- rising edge if SIGNAL’event and SIGNAL = ’0’ -- falling edge if NOT SIGNAL’stable and SIGNAL = ’0’ -- falling edge 2. Wait 문을 이용한 CLK 의 표현 wait until CLK = ’1’; -- rising edge triggered wait until CLK = ’0’;--falling edge triggered

VHDL Mealy and Moore model In general, the following guidelines apply when we describe the clock : Synchronous processes (processes that compute values only on clock edges) must be sensitive to the clock signal. Use wait-until or if. Asynchronous processes (processes that compute values on clock edges and when asynchronous conditions are TRUE) must be sensitive to the clock signal (if any), and to inputs that affect asynchronous behavior. Use “if” only.

VHDL Mealy and Moore model Mealy Machine Example 0/00 S0 S1 입력 : I 출력 : Y1, Y2 2 개의 process 문을 이용하여 표현 0/01 1/10 1/00

VHDL Mealy and Moore model Library ieee; Use ieee.std_logic_1164.all; ENTITY Meal IS PORT(clk : IN STD_LOGIC; reset : IN STD_LOGIC; I : IN STD_LOGIC; Y1, Y2 : OUT STD_LOGIC); END Meal; ARCHITECTURE a OF Meal IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk, reset) IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS WHEN s0 => IF I='1' THEN state <= s1; ELSE state <= s0; END IF; WHEN others => IF I='0' THEN state <= s0; ELSE state <= s1; END CASE;

VHDL Mealy and Moore model END IF; END PROCESS; PROCESS(state, I) BEGIN if( state= s0 and I='1') then Y1 <='1'; else Y1 <='0'; end if; if( state= s1 and I='0') then Y2 <='1'; Y2 <='0'; END a;

VHDL Mealy and Moore model Moore Machine Example 입력 : I 출력 : Y(2:0) 2 개의 process 문을 이용하여 표현 S0 000 1 S1 010 1 1 S2 101

VHDL Mealy and Moore model Library ieee; Use ieee.std_logic_1164.all; ENTITY Moor IS PORT(clk : IN STD_LOGIC; reset : IN STD_LOGIC; I : IN STD_LOGIC; y : OUT STD_LOGIC_vector(2 downto 0)); END Moor; ARCHITECTURE a OF Moor IS TYPE STATE_TYPE IS (s0, s1,s2); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk, reset) IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS WHEN s0 => IF I='1' THEN state <= s1; ELSE END IF;

VHDL Mealy and Moore model WHEN s1 => IF I='1' THEN state <= s2; ELSE state <= s1; END IF; WHEN others => state <= s0; END CASE; END PROCESS; PROCESS (state) BEGIN CASE state IS WHEN s0 => y <= "000"; WHEN s1 => y <= "010"; WHEN others => y <= "101"; END CASE; END PROCESS; END a;