1. State Machine & Timing Design

2. 강의 내용 Finite State Machine(FSM) FSM in VHDL More VHDL codes for FSMs
Mealy Machine
Moore Machine
FSM in VHDL
More VHDL codes for FSMs
Techniques for simple sequential logic design
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3. Finite State Machines (FSMs)
Any circuit with memory is a finite state machine (FSM:유한 상태 기계)
Even computers can be viewed as huge FSMs
Design of FSMs involves
Defining states
Defining transitions between states
Optimization / minimization
Manual optimization/minimization is practical for small FSMs only
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4. Present State register
Moore FSM
Output is a function of a present state only
Present State register
Next State
function
Output
Inputs
Present State
Outputs
clock
reset
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5. Moore Machine transition condition 1 state 2 / state 1 / output 2
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6. Present State register
Mealy FSM
Output is a function of a present state and inputs
Next State
function
Output
Inputs
Present State
Outputs
Present State register
clock
reset
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7. transition condition 1 / transition condition 2 /
Mealy Machine
transition condition 1 /
output 1
state 2
state 1
transition condition 2 /
output 2
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8. Moore vs. Mealy FSM (1)
Moore and Mealy FSMs can be functionally equivalent
Equivalent Mealy FSM can be derived from Moore FSM and vice versa
Mealy FSM has richer description and usually requires smaller number of states
Smaller circuit area
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9. Moore vs. Mealy FSM (2)
Mealy FSM computes outputs as soon as inputs change
Mealy FSM responds one clock cycle sooner than equivalent Moore FSM
Moore FSM has no combinational path between inputs and outputs
Moore FSM is more likely to have a shorter critical path
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10. Moore FSM - Example 1 Moore FSM that recognizes sequence “10” S0 / 01
reset
Meaning
of states:
S0: No
elements
of the
sequence
observed
S1: “1”
S2: “10”
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11. Mealy FSM - Example 1 Mealy FSM that recognizes sequence “10” S0 S1
0 / 0
1 / 0
0 / 1
reset
Meaning
of states:
S0: No
elements
of the
sequence
observed
S1: “1”
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12. Moore & Mealy FSMs – Example 1
clock
input
Moore
Mealy
S S S S S0
S S S S S0
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13. FSMs in VHDL
Finite state machines can be easily described with processes
Synthesis tools understand FSM description if certain rules are followed
State transitions should be described in a process sensitive to clock and asynchronous reset signals only
Outputs described as concurrent statements outside the process
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14. State Machine - Mealy Machine
현재의 상태(Current State)와 현재의 입력(Inputs)에 의해 출력이 결정됨
Combinational
Logic
F/F
Inputs
Outputs
Current State
Next State
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15. Mealy FSM 의 해석 – State diagram
0/00
1/00
0/01
1/10
WindowAct / RiseShot, FallShot
입력 / 출력1, 출력2
Reset 해석
1. WindowAct신호가 0에서 1로 변하면 S1 state으로 전환, 이 때 output RiseShot을 1로,
2. WindowAct신호가 1에서 0으로 변하면 S0 state으로 전환, FallShot을 1로 만들어야 함.
3. State 전환이 없으면 output들은 모두 0
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16. Mealy Machine 구현 – Process 2개사용
Library ieee; Use ieee.std_logic_1164.all;
ENTITY RiseFallShot IS
PORT( clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
WindowAct : IN STD_LOGIC;
RiseShot, FallShot : OUT STD_LOGIC);
END RiseFallShot;
ARCHITECTURE a OF RiseFallShot IS
TYPE STATE_TYPE IS (s0, s1);
SIGNAL state: STATE_TYPE;
BEGIN
PROCESS (clk, reset)
IF reset = '0' THEN
state <= s0;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN s0 =>
IF WindowAct='1' THEN
state <= s1;
ELSE
END IF;
WHEN others =>
IF WindowAct='0' THEN
END CASE;
END PROCESS;
새로운 Data type “STATE_TYPE” 지정
같은 부분
Current State
Combinational
Logic
F/F
Next State
Inputs
Combinational
Logic
Outputs
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17. Mealy Machine 구현 – Process 2개 사용
PROCESS(state, WindowAct)
BEGIN
if( state= s0 and WindowAct='1') then
RiseShot <='1';
else
RiseShot <='0';
end if;
if( state= s1 and WindowAct='0') then
FallShot <='1';
FallShot <='0';
END PROCESS;
END a;
Current State
Combinational
Logic
F/F
Next State
Inputs
Combinational
Logic
Outputs
같은 부분
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18. Mealy Machine 구현 – Process 3개 사용
library ieee;
Use ieee.std_logic_1164.all;
ENTITY RiseFallShot_v2 IS
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
WindowAct : IN STD_LOGIC;
RiseShot, FallShot : OUT STD_LOGIC);
END RiseFallShot_v2;
ARCHITECTURE a OF RiseFallShot_v2 IS
TYPE STATE_TYPE IS (s0, s1);
SIGNAL State, NextState: STATE_TYPE;
BEGIN
PROCESS (State, WindowAct)
CASE State IS
WHEN s0 =>
IF WindowAct='1' THEN
NextState <= s1;
ELSE
NextState <= s0;
END IF;
WHEN others =>
IF WindowAct='0' THEN
END CASE;
END PROCESS;
같은 부분
Current State
Combinational
Logic
F/F
Next State
Inputs
Combinational
Logic
Outputs
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19. Mealy Machine 구현 – Process 3개 사용
PROCESS(reset,clk)
BEGIN
IF reset = '0' THEN
State <= s0;
ELSIF clk'EVENT AND clk = '1' THEN
State <= NextState;
END IF;
END PROCESS;
process(State,WindowAct)
begin
if( State= s0 and WindowAct='1') then
RiseShot <='1';
else
RiseShot <='0';
end if;
if( State= s1 and WindowAct='0') then
FallShot <='1';
FallShot <='0';
end process;
같은 부분
Current State
Combinational
Logic
F/F
Next State
Inputs
Combinational
Logic
Outputs
같은 부분
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20. State Machine - Moore Machine
현재의 상태(Current State)만에 의해 출력(Outputs)이 결정됨
“Moore is less”
Current State
Combinational
Logic
F/F
Next State
Inputs
Combinational
Logic
Outputs
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21. Moore Machine 해석 – State diagram상태 출력 S0
000 S1
010 1 S2
101
Reset
입력 : WindowAct
출력 : y(2:0) 해석
1. WindowAct신호가 0일 때는 State의 변화가 없으며, 1일 때는 state의 변화가 S0->S1->S2->S0로 순환한다.
2. 출력신호 y(2:0)은 상태가 S0인 경우 “000”을 S1인 경우에는 “010”을 S2인 경우에는 “101”을 출력한다.
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22. Moore Machine 구현 – Process 2개 사용
Library ieee; Use ieee.std_logic_1164.all;
ENTITY MooreMachine IS
PORT( clk, reset, WindowAct : IN STD_LOGIC;
y : OUT STD_LOGIC_vector(2 downto 0));
END MooreMachine;
ARCHITECTURE a OF MooreMachine IS
TYPE STATE_TYPE IS (s0, s1,s2);
SIGNAL state: STATE_TYPE;
BEGIN
PROCESS (clk, reset)
IF reset = '0' THEN
state <= s0;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN s0 =>
IF WindowAct='1' THEN state <= s1;
ELSE state <= s0;
END IF;
WHEN s1 =>
IF WindowAct='1' THEN state <= s2;
ELSE state <= s1;
WHEN others =>
IF WindowAct='1' THEN state <= s0;
ELSE state <= s2;
END CASE;
END PROCESS;
같은 부분
Current State
Combinational
Logic
F/F
Next State
Inputs
Combinational
Logic
Outputs
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23. Moore Machine 구현 – Process 2개 사용
PROCESS(state)
BEGIN
CASE state IS
WHEN s0 =>
y <= "000";
WHEN s1 =>
y <= "010";
WHEN others =>
y <= "101";
END CASE;
END PROCESS;
END a;
Current State
Combinational
Logic
F/F
Next State
Inputs
Combinational
Logic
Outputs
같은 부분
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24. Moore Machine 구현 – Process 3개 사용
Library ieee; Use ieee.std_logic_1164.all;
ENTITY MooreMachine_v3 IS
PORT( clk, reset, WindowAct : IN STD_LOGIC;
y : OUT STD_LOGIC_vector(2 downto 0));
END MooreMachine_v3;
ARCHITECTURE a OF MooreMachine_v3 IS
TYPE STATE_TYPE IS (s0, s1,s2);
SIGNAL state, NextState: STATE_TYPE;
BEGIN
PROCESS ( State, WindowAct)
CASE State IS
WHEN s0 =>
IF WindowAct='1' THEN NextState <= s1;
ELSE NextState <= s0;
END IF;
WHEN s1 =>
IF WindowAct='1' THEN NextState <= s2;
ELSE NextState <= s1;
WHEN others =>
IF WindowAct='1' THEN NextState <= s0;
ELSE NextState <= s2;
END CASE;
END PROCESS;
같은 부분
Current State
Combinational
Logic
F/F
Next State
Inputs
Combinational
Logic
Outputs
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25. Moore Machine 구현 – Process 3개 사용
같은 부분
PROCESS (clk, reset)
BEGIN
IF reset = '0' THEN
state <= s0;
ELSIF clk'EVENT AND clk = '1' THEN
state <= NextState;
END IF;
END PROCESS;
PROCESS(state)
CASE state IS
WHEN s0 =>
y <= "000";
WHEN s1 =>
y <= "010";
WHEN others =>
y <= "101";
END CASE;
END a;
Current State
Combinational
Logic
F/F
Next State
Inputs
Combinational
Logic
Outputs
같은 부분
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26. Present State Register
Moore FSM
process(clock, reset)
Inputs
Next State
function
Next State
clock
Present State Register
Present State
reset
concurrent
statements
Output
function
Outputs
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27. Present State Register
Mealy FSM
process(clock, reset)
Inputs
Next State
function
Next State
Present State
clock
Present State Register
reset
Output
function
Outputs
concurrent
statements
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28. Moore FSM - Example 1 Moore FSM that Recognizes Sequence “10” S0 / 01
reset
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29. Moore FSM in VHDL (1) TYPE state IS (S0, S1, S2);
SIGNAL Moore_state: state;
U_Moore: PROCESS (clock, reset)
BEGIN
IF(reset = ‘1’) THEN
Moore_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Moore_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Moore_state <= S1;
ELSE
END IF;
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30. Moore FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN
Moore_state <= S2;
ELSE
Moore_state <= S1;
END IF;
WHEN S2 =>
Moore_state <= S0;
END CASE;
END PROCESS;
Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
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31. Mealy FSM - Example 1 Mealy FSM that Recognizes Sequence “10” S0 S1
0 / 0
1 / 0
0 / 1
reset
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32. Mealy FSM in VHDL (1) TYPE state IS (S0, S1);
SIGNAL Mealy_state: state;
U_Mealy: PROCESS(clock, reset)
BEGIN
IF(reset = ‘1’) THEN
Mealy_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Mealy_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Mealy_state <= S1;
ELSE
END IF;
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33. Mealy FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN
Mealy_state <= S0;
ELSE
Mealy_state <= S1;
END IF;
END CASE;
END PROCESS;
Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;
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34. Moore FSM – Example 2: State diagramC z 1 =
resetn B A w
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35. Moore FSM – Example 2: State table
Present
Next state
Output
state w = 1 z A B C
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36. Moore FSM with 2’s Processes
process(clock, reset)
Input: w
Next State
function
Next State
clock
Present State Register
Present State: y
resetn
concurrent
statements
Output: z
Output
function
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37. Moore FSM – Example 2: VHDL code (1)
USE ieee.std_logic_1164.all ;
ENTITY simple IS
PORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ;
w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;
END simple ;
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( resetn, clock )
IF resetn = '0' THEN
y <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
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38. Moore FSM – Example 2: VHDL code (2)
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
WHEN B =>
y <= C ;
WHEN C =>
END CASE ;
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39. Moore FSM – Example 2: VHDL code (3)
END IF ;
END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
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40. Moore FSM with 3’s Processes
y_present)
Input: w
Next State
function
Next State: y_next
process
(clock,
resetn)
Present State Register
clock
Present State:
y_present
resetn
concurrent
statements
Output
function
Output: z
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41. Alternative VHDL code (1)
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C) ;
SIGNAL y_present, y_next : State_type ;
BEGIN
PROCESS ( w, y_present )
CASE y_present IS
WHEN A =>
IF w = '0' THEN
y_next <= A ;
ELSE
y_next <= B ;
END IF ;
WHEN B =>
y_next <= C ;
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42. Alternative VHDL code (2)
WHEN C =>
IF w = '0' THEN
y_next <= A ;
ELSE
y_next <= C ;
END IF ;
END CASE ;
END PROCESS ;
PROCESS (clock, resetn)
BEGIN
IF resetn = '0' THEN
y_present <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
y_present <= y_next ;
z <= '1' WHEN y_present = C ELSE '0' ;
END Behavior ;
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43. Mealy FSM – Example 2: State diagramw = z / 1 B
resetn
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44. Mealy FSM – Example 2: State table
Present
Next state
Output z
state w = 1 A B
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45. Mealy FSM with 2’s Processes
process(clock, reset)
Input: w
Next State
function
Next State
Present State: y
Present State Register
clock
resetn
Output
function
Output: z
concurrent
statements
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46. Mealy FSM – Example 2: VHDL code (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Mealy IS
PORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ;
w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;
END Mealy ;
ARCHITECTURE Behavior OF Mealy IS
TYPE State_type IS (A, B) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( resetn, clock )
IF resetn = '0' THEN
y <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
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47. Mealy FSM – Example 2: VHDL code (2)
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
WHEN B =>
END CASE ;
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48. Mealy FSM – Example 2: VHDL code (3)
END IF ;
END PROCESS ;
WITH y SELECT
z <= w WHEN B,
z <= ‘0’ WHEN others;
END Behavior ;
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49. Timing Design - 강의순서 State Machine 응용 Shift Register 응용 Counter 응용
주어진 타이밍도로부터 회로를 설계하는 방법을 다양한 형태의 접근 방법을 통해 습득한다. 각종 디바이스의 데이터 북상에 나타나는 타이밍 도의 이해를 위한 더욱 심화된 지식을 배양한다.
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50. Timing Design – State Machine Application (1)
해석 : WindowAct신호가 0에서 1로 변하는 순간부터 다음 clock의 rising edge 까지 RiseShot을 1로 만들고
WindowAct신호가 1에서 0으로 변하는 순간부터 다음 clock의 rising edge 까지 FallShot을 1로 만들어야 함.
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51. Timing Design – State Machine Application (2)
2.Excercise: Mealy-machine state diagram을 완성하라 S0 S1
0/00
1/00
0/01
1/10
WindowAct / RiseShot, FallShot
입력 / 출력1, 출력2
모바일컴퓨터특강

52. Timing Design – State Machine Application (3)
상태도에서 입력에 따른 상태의 변화만을 기술 S0 S1
0/00
1/00
0/01
1/10
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53. Timing Design – State Machine Application (4)
0/00
1/00
0/01
1/10
상태도에서 입력에 따른 출력의 변화만을 기술
Note: The outputs react to input asynchronously.
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54. Timing Design – State Machine Application (5)
Result
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55. Timing Design – State Machine Application (6)
3. 상태도를 이용하지 않는 다른 방법은 ?
 Timing 만을 고려한 설계 1 3 4 2
1,3 에서
RiseShot= WindowAct and Q’
Q는 WindowAct를 D F/F으로 통과시킨 출력
2,4 에서
FallShot= WindowAct’ and Q
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56. Timing Design – State Machine Application (7)
3. Timing 만을 고려한 설계방식 - BDF
Q는 WindowAct를 D FF으로 통과시킨 출력
WindowAct and Q’
not Q
not WindowAct
모바일컴퓨터특강
WindowAct’ and Q

57. Timing Design – State Machine Application (8)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RiseFallShot_time is
port( WindowAct : in std_logic;
clk,nclr : in std_logic;
RiseShot,FallShot : out std_logic );
end RiseFallShot_time;
architecture a of RiseFallShot_time is
signal q : std_logic;
signal RisingShotPules : std_logic;
begin
-- shift register 1bits
process(nclr,clk)
if( nclr='0') then
q <='0';
elsif(clk'event and clk='1') then
q <= WindowAct;
end if;
end process;
-- rising shot pulse gen.
RiseShot <= WindowAct and not q;
FallShot <= not WindowAct and q;
end a;
3. Timing 만을 고려한 설계방식 - VHDL
같은 회로
같은 회로
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58. Timing Design – Shift Register Application (1)
입력신호 : reset, clk, WindowAct
출력신호 : y0, y1, y2, y3, y4, y5, y6
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59. Timing Design – Shift Register Application (2)
1. 먼저 아래의 회로를 만들어보자.
입력신호 : reset, clk, WindowAct
출력신호 : y0
어떤 방식으로 설계해야 하는가?
 1차적으로 생각할 수 있는 방법은 Shift Register를 이용하는 방법
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60. Timing Design – Shift Register Application (3)
출력신호 y0는 Q1가 1이 되는 부분과 Q2가 0이 되는 ns부분에서 1이 된다.
Y0=Q1 and Q2’
그림과 같은 Shift Register를 사용하게 되면 Q0, Q1, Q2의 타이밍을 예상할 수 있다.
Y0 = Q1 and not Q2
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61. Timing Design – Shift Register Application (4)
2. 이번에는 y1을 만들어보자.
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62. Timing Design – Shift Register Application (5)
Y0를 clk의 falling edge를 이용하여 shift하면 반클럭 shift된 Y1을 만들 수 있다.
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63. Timing Design – Shift Register Application (6)
3. 이번에는 y2를 만들어보자.
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64. Timing Design – Shift Register Application (7)
Y2는 Y0와 Y1을 OR 한 것임을 알 수 있다.
Y2 = Y0 or Y1
Y2 = Y0 or Y1
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65. Timing Design – Shift Register Application (8)
4. 이번에는 y3을 만들어보자.
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66. Timing Design – Shift Register Application (9)
11 bits Shift Register
Y3는 11개의 shift register중에서 Q9가 1이면 Q10이 0인 구간에 1이 출력되는 신호.
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67. Timing Design – Shift Register Application (10)
Y3는 11개의 shift register중에서 Q10과 Q9를 이용한 신호임.
Y3 = Q9 and Q10’
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68. Timing Design – Shift Register Application (11)
5. 이번에는 y4을 만들어보자.
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69. Timing Design – Shift Register Application (12)
Y4는 Y1와 Y3을 OR 한 것임을 알 수 있다.
Y4 = Y1 or Y3
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70. Timing Design – Shift Register Application (13)
6. 이번에는 y5을 만들어보자.
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71. Timing Design – Shift Register Application (14)
Y5는 Q2가 1이며 Q10이 0인 구간에 1을 출력.
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72. Timing Design – Shift Register Application (15)
7. 이번에는 y6을 만들어보자.
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73. Timing Design – Shift Register Application (16)
Y6p는 Q1이 1이며 Q9가 0인 구간에 1을 출력.
Y6는 Y6p를 Clk의 Falling Edge를 이용하여 반 클럭 밀어준 신호임.
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74. Timing Design – Shift Register Application (17)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shift_app2 is
port( clk,nclr,WindowAct : in std_logic;
y : buffer std_logic_vector(0 to 6));
end shift_app2;
architecture a of shift_app2 is
signal q : std_logic_vector(0 to 10);
signal y6p : std_logic;
begin
ShiftRegster :
process(nclr,clk)
if( nclr='0') then
q<=" ";
elsif(clk'event and clk='1') then
q(0)<= WindowAct;
for i in 0 to 9 loop
q(i+1) <= q(i);
end loop;
end if;
end process;
y(0) <= q(1) and not q(2);
동일회로
동일회로
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75. Timing Design – Shift Register Application (18)
동일회로
process(nclr,clk)
begin
if( nclr='0') then
y(1)<='0';
elsif(clk'event and clk='0') then
y(1)<=y(0);
end if;
end process;
y(2) <= y(0) or y(1);
y(3) <= q(9) and not q(10);
y(4) <= y(1) or y(3);
y(5) <= q(2) and not q(10);
y6p <= q(1) and not q(9);
y(6)<='0';
y(6)<=y6p;
end a;
동일회로
동일회로
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76. Timing Design – Result (1)
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77. Timing Design – Result (2)
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78. Timing Design – Resource Usage
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79. Timing Design – Counter Application (1)
아래와 같은 Timing 입출력 파형을 갖는 회로를 Shift Register가 아닌 다른 방식(Counter응용)으로 설계해보자.
입력신호 : reset, clk, WindowAct
출력신호 : y0, y1, y2, y3, y4, y5, y6
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80. Timing Design – Counter Application (2)
1. 입력신호 들로부터 cnt[3..0]을 만들 수 있는가?
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81. Timing Design – Counter Application (3)
이 카운터는 WindowAct가 1일 때만 증가되며, WindowAct가 0일 때는 0으로 된다.
process(nclr,clk)
begin
if( nclr='0') then
cnt<="0000";
elsif(clk'event and clk='1') then
if(WindowAct='0') then
else
cnt <= cnt+1;
end if;
end process;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt_app2 is
port( clk,nclr,WindowAct : in std_logic;
y : buffer std_logic_vector(0 to 6));
end cnt_app2;
architecture a of cnt_app2 is
signal cnt : std_logic_vector(3 downto 0);
begin
Cnt 회로
Cnt[3..0]을 사용
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82. Timing Design – Counter Application (4)
2. 입력신호 들과 cnt[3..0]로 부터 Y0, Y3을 만들 수 있는가?
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83. Timing Design – Counter Application (5)
Y0 발생부
Y3 발생부
process(cnt)
begin
if( cnt=2) then
y(0)<='1';
else
y(0)<='0';
end if;
end process;
process(cnt)
begin
if( cnt=10) then
y(3)<='1';
else
y(3)<='0';
end if;
end process;
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84. Timing Design – Counter Application (6)
3. Y1,Y2,Y4의 발생은?
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85. Timing Design – Counter Application (7)
process(nclr,clk)
begin
if( nclr='0') then
y(1)<='0';
elsif(clk'event and clk='0') then
y(1)<=y(0);
end if;
end process;
y(2) <= y(0) or y(1);
y(4) <= y(1) or y(3);
Y0를 clk의 falling edge를 이용하여 시프트하면 반클럭 시프트된Y1을 만들 수 있다.
Y2는 Y0와 Y1을 OR 한 것임을 알 수 있다.
Y2 = Y0 or Y1
Y4는 Y1와 Y3을 OR 한 것임을 알 수 있다.
Y2 = Y0 or Y1
Y2,Y4발생부
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86. Timing Design – Counter Application (8)
4. Y5,Y6의 발생은?
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87. Timing Design – Counter Application (9)
process(nclr,clk)
begin
if( nclr='0') then
y(5)<='0';
elsif(clk'event and clk='1') then
if(cnt=2) then
y(5)<='1';
elsif(cnt=10) then
else
y(5)<=y(5);
end if;
end process;
Y5발생부 : Cnt=2일 때 1로 변하고 Cnt=0일 때 0으로 변한다. Clk의 rising Edge기준
process(nclr,clk)
begin
if( nclr='0') then
y(6)<='0';
elsif(clk'event and clk='0') then
if(cnt=2) then
y(6)<='1';
elsif(cnt=10) then
else
y(6)<=y(6);
end if;
end process;
end a;
Y6발생부 : Cnt=2일 때 1로 변하고 Cnt=0일 때 0으로 변한다. Clk의 Falling Edge기준
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88. Timing Design – Result (1)
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89. Timing Design – Result (2)
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90. Timing Design – Result (3)
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