1. Integer Square Root

2. Integer Square Root
unsigned long sqrt(unsigned long a){ unsigned long square = 1;
unsigned long delta = 3;
while(square <= a){
square += delta;
delta += 2; }
return (delta/2 - 1);

3. Integer Square Root unsigned long sqrt(unsigned long a){
unsigned long square = 1;
unsigned long delta = 3;
while(square <= a){
square += delta;
delta += 2; }
return (delta/2 - 1);

4. Integer Square Root

5. Datapath
unsigned long sqrt(unsigned long a){
unsigned long square = 1;
unsigned long delta = 3;
while(square <= a){
square += delta;
delta += 2; }
return (delta/2 - 1);
The following steps can be used to create a datapath for implementing an algorithm.
Draw a register (rectangular box with input at the top and output at the bottom) for each variable in the algorithm. For the algorithm in Listing 1 these would include a, square, delta, and outreg (for the return value). Each register will also have a reset, clock, and load inputs. When the reset signal is high, the output of the register will be a predetermined initial value. If the load signal is high, then on the next rising edge of the clock signal the input value will be loaded into the register and appear on the output.
Define combinational blocks to implement any necessary arithmetic or logical operation.
Connect the outputs of the registers to the inputs of the appropriate arithmetic and logical operations, and connect the outputs of the arithmetic and logical operations to the appropriate registers. Multiplexers can be used if the input to a register can come from more than one source.

7. State Diagrams unsigned long sqrt(unsigned long a){
unsigned long square = 1;
unsigned long delta = 3;
while(square <= a){
square += delta;
delta += 2; }
return (delta/2 - 1);

8. A Moore state machine

9. SQRTctl unsigned long sqrt(unsigned long a){ unsigned long square = 1;
unsigned long delta = 3;
while(square <= a){
square += delta;
delta += 2; }
return (delta/2 - 1);

11. SQRTctl.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SQRTctrl is
Port ( clk : in std_logic;
clr : in std_logic;
lteflg : in std_logic;
go : in std_logic;
ald : out std_logic;
sqld : out std_logic;
dld : out std_logic;
outld : out std_logic;
states : out std_logic_vector(1 downto 0));
end SQRTctrl;
states(1:0)

12. A Moore state machine

13. SQRTctl.vhd (cont.) architecture Behavioral of SQRTctrl is
type state_type is (start, test, update, done);
signal present_state, next_state: state_type;
begin
synch: process(clk, clr)
if clr = '1' then
present_state <= start;
elsif clk'event and clk = '1' then
present_state <= next_state;
end if;
end process;

14. A Moore state machine

15. SQRTctl.vhd (cont.) C1: process(present_state, go, lteflg) begin
case present_state is
when start =>
if go = '1' then
next_state <= test;
else
next_state <= start;
end if;
when test =>
if lteflg = '1' then
next_state <= update;
next_state <= done;
when update =>
when done =>
when others =>
null;
end case;
end process;

16. A Moore state machine

17. SQRTctl.vhd (cont.) C2: process(present_state) begin
ald <= '0'; sqld <= '0';
dld <= '0'; outld <= '0';
states <= "00";
case present_state is
when start =>
ald <= '1'; states <= "00";
when test =>
states <= "01";
when update =>
sqld <= '1'; dld <= '1'; states <= "10";
when done =>
outld <= '1'; states <= "11";
when others =>
ald <= '0'; sqld <= '0'; dld <= '0';
outld <= '0'; states <= "00";
end case;
end process;
end Behavioral;