1. ACANEL VHDL 의 이해와 실습 2000 년 1 학기 Computer Architecture http://www.cs.hongik.ac.kr/~yhchoi (classes links)

2. ACANEL Introduction  VHDL  VHSIC(Very High Speed Integrated Circuit) Hardware Description Language  VHDL 의 특성  Device-Independent Design  Benchmarking Capabilities  Quick Time-to-Market and Low Cost

3. ACANEL Introduction  Using VHDL for design synthesis  Define the design requirement  Describe the design in VHDL  Simulate the source code  Synthesize, optimize, and fit(place and route) the design  Simulate the post-layout design model  Program the device

4. ACANEL Introduction Design Idea Behavioral Design Data Path Design Logic Design Physical Design Manufacturing Chip or Board Flow Graph, Pseudo Code Bus & Register Structure Gate Wirelist, Netlist Transister List, Layout A digital system design process.

5. ACANEL VHDL Syntax  Design entity  설계의 최소단위  Entity & Architecture  Package  Library  Configuration declaration

6. ACANEL Entity  Declaration.  Entity 는 설계의 component 의 이름과 input/output port interface 를 정의하고 동작에 필요한 parameter 를 전달한다.  내부 동작을 고려하지 않고 외부적인 모습만을 설계한다.  Format. Entity entity_name is generic (parameter_list); port(parameter_list); declaration; begin statements End entity_name; Entity OR2 is port(I1,I2 : in bit; O : out bit); End OR2; I1 I2 O2

7. ACANEL Entity  Generic  To design parameterized components, for which the size and features sets may be defined by values of the instant parameters.  Ports  Entity 의 I/O 를 표현.  Data type : Bit, Bit_vector, Byte, integer, IEEE std_logic_1164.  Mode : in, out, inout, buffer, linkage  In : input signal  Out : output signal  Inout : in + out  Buffer : entity 의 결과 signal 을 다시 입력으로 이용, 외부입력 불가

8. ACANEL Entity  Declaration  여러 Architecture 에서 공통으로 사용되는 것들을 선언.  Example Library ieee; Use ieee.std_logic_1164.all; Entity add4 is generic ( bit_size : positive); port(a,b : in std_logic_vector(bit_size downto 0); ci : in std_logic; sum : out std_logic_vector(bit size downto 0); co : out std_logic); End add4;

9. ACANEL Architecture  Architecture bodies  An architecture describes the contents of an entity  하나의 entity 선언에 여러 개의 architecture 사용 가능  Format Architecture arch_name of entity_name is declaration Begin internal behavior description End arch_name;

10. ACANEL Architecture  Behavioral Description  시스템의 동작을 Algorithm level 에서 H/W 와 관계없이 표현 Architecture behavioral of eqcomp4 is Begin comp: process (a, b) begin equals <= ‘0’; if a = b then equals <= ‘1’; end if; end process comp; End behavioral;

11. ACANEL Architecture  Dataflow Description  시스템을 자료의 흐름에 맞추어 설계 Architecture dataflow of eqcomp4 is Begin equals <= ‘1’ when (a=b) else ‘0’; End dataflow;

12. ACANEL Architecture  Structural Description  각각의 구조를 component 로 나타내고 이들간의 연결로 시스템 을 표현. Architecture structural of eqcomp4 is Begin signal x : std_logic_vector(0 to 3); u0 : xnor2 port map (a(0), b(0),x(0)); u1 : xnor2 port map (a(1), b(1),x(1)); u2 : xnor2 port map (a(2), b(2),x(2)); u3 : xnor2 port map (a(3), b(3),x(3)); u4 : and4 port map (x(0), x(1),x(2), x(3),equals); end structural; a b

13. ACANEL Statements  Sequential statements  내부의 동작을 순차적으로 표현  Process Statements 이용  각각의 process 문은 concurrent 하게 동작  Concurrent statements  시스템의 동작표현 시 이용

14. ACANEL Sequential Statements  Wait Statements  Wait on signal_list; -- signal_list : process 의 sensitive list  Wait until condition; -- condition 이 true 일때까지 wait  Wait for time; -- time 만큼의 시간동안 wait  Wait; -- 수행 중지  Signal Assignment Statements  Signal_name <= value -- no delay time(delta delay)  Signal_name <= value after delay_time;

15. ACANEL Sequential Statements  If statements If cond1 then statement1 Elsif cond2 then statement2 Else statement3 End if; Process Begin if x = ‘0’ and y=‘0’ then z <= ‘1’ after 3ns; elsif x = ‘X’ or y = ‘X’ then z <= ‘1’ after 3ns; else z <= ‘0’ after 3ns; end if; wait on x,y; End process;

16. ACANEL Sequential Statements  Case Statements Case 수식 is when value1 => statement1; when value2 => statement2; when others => statement3; end case; Process Begin case sel is when “00” => z <= in0 after 5ns; when “01” => z <= in1 after 5ns; when “10” => z <= in2 after 5ns; when “11” => z <= in3 after 5ns; wait on sel; End process;

17. ACANEL Data Objects  Constant,signal,variable  Constant : 선언할 때 값을 정한 뒤, 바꿀 수 없다.  Signal : 값 대입시 미래의 어느 시점에 값이 바뀐다.  Variable : 값이 그 즉시 대입된다. Constant Delay : Time := 5ns; Variable va : Integer; Signal Clock, Set Clear : bit; va := 30; Set <= ‘1’;

18. ACANEL Design Example  MUX 4x1 Library IEEE; Use IEEE.std_logic_1164.all; Entity mux is port ( a,b,c,d : in std_logic_vector(3 downto 0); s : in std_logic(1 downto 0); x : out std_logic_vector(3 downto 0)); End mux; Architecture archmux of mux is Begin x <= a when (s = “00”) else b when (s = “01”) else c when (s = “10”) else d; End archmux;

19. ACANEL Design Example  Test bench for MUX 4x1 (2bit)

20. ACANEL Design Example  8-bit Register Library IEEE; Use IEEE.std_logic_1164.all; Entity reg_logic is port ( d : in std_logic_vector(0 to 7); reset, init clk : in std_logic; q : out std_logic_vector(0 to 7)); End reg_logic; Architecture archreg2 of reg_logic is Begin process(clk, reset) begin if (reset = ‘1’) then q <= “00000000”; elsif (clk’event and clk = ‘1’) then if (init <= ‘1’) then q <= “11111111”; else q <= d; end if; end process;