Sandia National Labs SAR ATR Hour for the SLAAC Fall ‘99 Retreat Intro/Module Performance Goals: Brian Bray FOA: Scott Hemmert SLD: Steve Crago CDI: Mike Wirthlin Wrap-up (Good/Bad/Future): Brian Bray

Sandia National Labs Current Challenge Problem Modules FOA (Focus of Attention) –adaptive rank order quantization and multi-level morphology –quad uP:~2 Mpixels/secACS goal: ~10 Mpixels/sec* SLD (Second Level Detection) –for in-the-clear scenarios –adaptive attenuation estimation with binary template matching –quad uP: ~16000 templates/secACS goal: ~80000 templates/sec CDI (Contamination Distribution Indexer) –for camouflage, concealment and deception (CC&D) scenarios –epsilon-contaminated mixtures model (~10X more compute intensive than SLD) –initial ACS goal is just the 2X not the 1X templates (90% of compute) –quad uP: ~1600 templates/sec Inital ACS goal: ~16000 templates/sec End ACS goal: (2X and 1X templates at ~80000 templates/sec) microprocessor = PowerPC 400Mhz *Mpixel in downsampled space

Sandia National Labs The Good ACS CDI Performance JHDL BYU students and faculty Virtex parts –on-chip memory –large amounts of logic

Sandia National Labs The Bad We are behind Need an embedded Virtex based ACS board ACS parts with large penalty for large precision and FP operations What is the third generation ACS part?

Sandia National Labs The Future (As I See It) Bigger second generation ACS parts and better tools will come –third generation will not be here in near term what will it be??? –Virtex-like with RISC core, I$, D$ and DRAM interface? –Will it be an improvement to compute tasks or just system on a chip applications PCI accelerator cards with multiprocessor workstation based groundstations –will reduce the need for embedded VME hardware –Annapolis Microsystems PCI WildSTAR is a significant improvement over WildForce –SLAAC PCI? When compared to the WildSTAR, what design features can a SLAAC PCI Virtex board provide to overcome not being COTS and available now? Daughtercards for embedded VME multicomputers –CSPI, Mercury many Mercury only shops for embedded VME multicomputers

Sandia National Labs Mercury Compatible ACS Node Race Series PowerPC CN ASIC SDRAM PowerPC L2$ Race Series PowerPC CN ASIC SDRAM PowerPC L2$ Race Series PowerPC CN ASIC SDRAM Virtex SRAM Virtex SRAM CLK Gen Boot EEPROM 64 Mercury’s PPC DaughtercardACS Daughtercard Can SLAAC get access to these chips and enough info to write SW drivers? Can this bus be run at a lower clock rate than 83.3Mhz? How do others go about designing Mercury compatible daughtercards?