1. Radar Processing with COTS Components
Jack M. West, Brian F. Veale, Jeffrey T. Muehring, and John K. Antonio Texas Tech University DARPA Contract No. F
Data Source
VME
Mercury
System CN PE
...
SPARC
Reconfigurable
Subsystem
DSP/GPP
Data Sink
Architecture of Prototype System
Annapolis
SAR Processing Flow
STAP Flow
Range
Compression
Azimuth
Processing
Range
Compression
Doppler
Filtering
Weight
Computation
PCI PC PC
120 MB/sec
120 MB/sec
120 MB/sec
Data
Transfer
Range
Data
Transfer
Range
Doppler
Azimuth Sectioned Convolutions
Azimuth
FFT Size
Data
Transfer
Channel
Overlap
Kernel
Size
Section
Research Topics
PCI MOTHER BOARD
PENTIUM
DRAM
WILD ONE
SRAM
ANNAPOLIS WILDFORCE
HARD DISK DRIVE CN
ASIC
RIN-T
VME BACKPLANE
MERCURY RACE MCH 9U BOARD
ANNAPOLIS WILD CHILD
SPARC
ROUT-T
FORCE SPARC 5V
Probabilistic Power Prediction Simulator for Xilinx 4000-series Parts
RACE Network Simulator
CN Configuration for SAR Processing
Series/Parallel FIR Design for FPGA- based Range Compression
Selection of FPGA Word Sizes and Formats
Mapping and Scheduling of STAP Data Communications
Weight Calculation Algorithm Selection and Integration with FPGA- based Inner Product Co-Processor
Minimal Power Configuration of FPGA/DSP/GPP System for STAP and SAR Processing
Physical View of Prototype System