1. RiceNIC: A Reconfigurable and Programmable Gigabit Network Interface Card Jeff Shafer, Dr. Scott Rixner Rice Computer Architecture: http://www.cs.rice.edu/CS/Architecture System Architecture Development Platform  Avnet Virtex-II Pro Development Board Serial Port RJ-45 Port DDR Virtex FPGA Spartan FPGA PCI InterfaceEthernet PHY Networks are Essential!  Networking is an integral part of computer systems  The role of a network interface is evolving  Significant new research is changing the hardware/software interface between the operating system and the network interface card (NIC)  Researchers need a flexible NIC to study this field  RiceNIC is a reconfigurable and programmable Gigabit Ethernet NIC that meets these research needs  NIC design is freely available for research/education!  NIC provides significant computation and storage resources and allows the user to customize NIC behavior in software and hardware.  Networking is an integral part of computer systems  The role of a network interface is evolving  Significant new research is changing the hardware/software interface between the operating system and the network interface card (NIC)  Researchers need a flexible NIC to study this field  RiceNIC is a reconfigurable and programmable Gigabit Ethernet NIC that meets these research needs  NIC design is freely available for research/education!  NIC provides significant computation and storage resources and allows the user to customize NIC behavior in software and hardware. Device Utilization  Space for future development ComponentVirtex FPGA Slice Registers9,089 / 27,39233% 4 input LUTs11,811 / 27,39243% BRAMs51 / 13637% Occupied Slices9,164 / 13,69666% Global Clocks10 / 1662% Clock Managers5 / 862% Gate Count:3,944,049 NIC Features  Software Programmability  Dual 300 MHz PowerPC processors  256 MB DDR memory  2MB SRAM (accessible from host and NIC)  Serial port for debugging  Descriptor control system  Hardware Acceleration  MAC / DMA controllers  TCP Checksum Offloading  Hardware Event notification  Software Programmability  Dual 300 MHz PowerPC processors  256 MB DDR memory  2MB SRAM (accessible from host and NIC)  Serial port for debugging  Descriptor control system  Hardware Acceleration  MAC / DMA controllers  TCP Checksum Offloading  Hardware Event notification PerformancePerformance  RiceNIC TCP stream throughput compared to commercial NIC Software Design  PowerPC processor runs custom packet-handling firmware  Interfaces with MAC to send/receive packets  Interfaces with DDR to store bulk frame data  Interfaces with DMA engine to transfer data to/from host  Custom Linux and FreeBSD device drivers  PowerPC processor runs custom packet-handling firmware  Interfaces with MAC to send/receive packets  Interfaces with DDR to store bulk frame data  Interfaces with DMA engine to transfer data to/from host  Custom Linux and FreeBSD device drivers Virtex FPGA Placement Ethernet MAC DDR Controller PCI DMA Engine NIC Control & Data Bus PowerPC Processors