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Hardware Overview Net+ARM – Well Suited for Embedded Ethernet

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Presentation on theme: "Hardware Overview Net+ARM – Well Suited for Embedded Ethernet"— Presentation transcript:

1 Hardware Overview Net+ARM – Well Suited for Embedded Ethernet
Single and Multiple Processor Environments Understand the System on a Chip Net+ARM Performance

2 Why the NET+ARM is Well Suited for Embedded Ethernet Projects …
ARM7 CPU Cache RAM Cache Utilization Cache Control Network Ethernet Serial ENI 1284 GPIO MEM & BUS DMA External RAM

3 NET+ARM™ System Overview Single Processor Environment
Power Reset FLASH SDRAM EDO DRAM FP DRAM SRAM Clock JTAG RAM Shared RAM FIFO Additional I/O Optional Co-Processor Interface Three Additional Chip Selects Available for External Hardware 8, 16, or 32 Bit Peripherals Independently Configured External Bus Master Capable ENI Interface UART, HDLC, SPI Supported… Serial Port Line Driver RS232, 422, 485 DMA Support JTAG Serial Port Line Driver DMA CAPABLE Network Serial Interface Physical Layer Transformer RJ45 DMA Support

4 NET+ARM™ System Overview Multiple Processor Environment
Data movement to / from external processor Power Reset FLASH JTAG SDRAM EDO DRAM FP DRAM SRAM RAM External Processor ENI Three Additional Chip Selects Available for External Hardware 8, 16, or 32 Bit Peripherals Independently Configured External Bus Master Capable FLASH RAM JTAG Shared RAM Up to 64K of NET+ARM RAM designated FIFO Two 32 Byte FIFOs supported by DMA NET+ARM ENI INTERFACE is a SLAVE Serial Interface DMA CAPABLE Network Physical Layer Transformer RJ45 DMA Support

5 Understanding the SoC Peripherals Peripherals DMA ENI ARM7 Core Bus
GEN Module Interrupt DMA ENI Timer GPIO Ethernet Controller ARM7 Core Cache Serial Controller Memory Controller Bus Controller Bus Arbiter Clock Peripherals

6 NET+ARM™ Performance (X32 SDRAM with Multiple DMA Channels)
BUS MASTERING TYPICAL DESIGN EACH BUS MASTER IN THE CURRENT CYCLE CAN MOVE 4 LONG WORDS… MUST THEN GIVE UP THE BUS IF ANOTHER BUS MASTER IS WAITING 11 11 11 POTENTIAL BUS MASTERS  ARM7 DMA ENI External NOTE 1 DMA1 ARM7 DMA1 ARM7 ARM7 DMA2 ARM7 DMA2 78 Mbytes / Sec 78 Mbytes / Sec 78 Mbytes / Sec 78 Mbytes / Sec 78 Mbytes / Sec 78 Mbytes / Sec 78 Mbytes / Sec 78 Mbytes / Sec WITH NO CACHE SAME CYCLE WITH CACHE DMA1 ARM7 DMA1 DMA1 ARM7 DMA1 ARM7 78 Mbytes / Sec 78 Mbytes / Sec 78 Mbytes / Sec 78 Mbytes / Sec 78 Mbytes / Sec OVER 2 CYCLES EQUATES TO … 78 Mbytes / Sec on DMA 78 Mbytes / Sec with ARM OVER 2 CYCLES EQUATES TO … 39 Mbytes / Sec 8.5 MIPS 78 Mbytes/Sec 40 MIPS Assuming Burst CACHE is Single Cycle Memory Frequency  MHz NOTE 1: DMA Context Switch Time  13 BCLKS

7 NET+ARM™ Performance (X32 SDRAM with 1 DMA Channel)
BUS MASTERING TYPICAL DESIGN EACH BUS MASTER IN THE CURRENT CYCLE CAN MOVE 4 LONG WORDS… MUST THEN GIVE UP THE BUS IF ANOTHER BUS MASTER IS WAITING POTENTIAL BUS MASTERS  ARM7 DMA ENI External 11 11 11 ARM7 DMA1 78 Mbytes / Sec ARM7 DMA1 78 Mbytes / Sec WITH NO CACHE OVER 2 CYCLES EQUATES TO … 8.8 MIPS 39 Mbytes / Sec ARM7 DMA1 78 Mbytes / Sec SAME CYCLE WITH CACHE 78 Mbytes / Sec on DMA 78 Mbytes / Sec with ARM OVER 2 CYCLES EQUATES TO … 40 MIPS 78 Mbytes/Sec Assuming Burst CACHE is Single Cycle Memory Frequency  MHz

8 NET+ARM™ Performance (X32 SRAM with 1 DMA Channel)
TYPICAL DESIGN EACH BUS MASTER IN THE CURRENT CYCLE CAN MOVE 4 LONG WORDS… MUST THEN GIVE UP THE BUS IF ANOTHER BUS MASTER IS WAITING POTENTIAL BUS MASTERS  ARM7 DMA ENI External ARM7 DMA 106 Mbytes / Sec ARM7 DMA 106 Mbytes / Sec WITH NO CACHE OVER 2 CYCLES EQUATES TO … 12 MIPS 53 Mbytes / Sec ARM7 DMA 106 Mbytes / Sec SAME CYCLE WITH CACHE 106 Mbytes / Sec on DMA 106 Mbytes / Sec with ARM OVER 2 CYCLES EQUATES TO … 40 MIPS 106 Mbytes/Sec Assuming Burst CACHE is Single Cycle Memory Frequency  MHz

9 NET+ARM™ Performance (X32 SRAM with Multiple DMA Channels)
TYPICAL DESIGN EACH BUS MASTER IN THE CURRENT CYCLE CAN MOVE 4 LONG WORDS… MUST THEN GIVE UP THE BUS IF ANOTHER BUS MASTER IS WAITING POTENTIAL BUS MASTERS  ARM7 DMA ENI External NOTE 1 DMA1 ARM7 DMA2 106 Mbytes / Sec DMA1 ARM7 106 Mbytes / Sec WITH NO CACHE OVER 2 CYCLES EQUATES TO … 8.5 MIPS 38 Mbytes / Sec DMA1 ARM 106 Mbytes / Sec SAME CYCLE WITH CACHE 106 Mbytes / Sec on DMA 106 Mbytes / Sec with ARM OVER 2 CYCLES EQUATES TO … 40 MIPS 106 Mbytes/Sec ARM7 Assuming Burst CACHE is Single Cycle Memory Frequency  MHz NOTE 1: DMA Context Switch Time  13 BCLKS

10 Hardware Overview Summary
Up to four bus masters: ARM7, DMA, ENI, External Bus master must relinquish the bus to another waiting master after four long words transferred Cache permits ARM7 to move data concurrently with DMA DMA cannot operate on cached memory DMA channel context switch requires 13 clock cycles


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