1. SAR-ATR/FOA Compiler for ACS SLAAC Retreat, March ‘99 Brad L. Hutchings Configurable Computing Lab Brigham Young University

2. Joint STARS ‘97 SAR ATR Pipeline Identification Indexer (SLD) Focus of Attention Detection Annotated SAR Image Belief Management (Fusion Executive) MPM CRMMSELPM.. Joint STARS Advance Workstation (JAWS) ATR Results Display PGA ESAR Image SAR Image T72 *Not Joint STARS imagery

3. Joint STARS ‘97 SAR ATR Pipeline Identification Indexer (SLD) Focus of Attention Detection Annotated SAR Image Belief Management (Fusion Executive) MPM CRMMSELPM.. Joint STARS Advance Workstation (JAWS) ATR Results Display PGA ESAR Image SAR Image T72 Sandia National Labs *Not Joint STARS imagery Binary Morphology AIQ

4. What the ATR programmer wants... ATR Guy quant 1 2 3 span 0 2 4 1 span 2 4 2 3 cover 4 0... Go-Fast Box TM No circuit design Automated mapping. Fast compile times. 10x or better performance. Wish List

5. What the ATR programmer gets… (current state of the art) ATR Guy Box of Gates TM Must be circuit designer. No automated mapping. Slow compile times (days). 10x or better performance. Yikes!

6. We are getting close to the ideal. (.def files in, bitstreams out). ATR Guy ACS Platform BYU-FOA Compiler FOA.def file (binary morphology) span 0 2 4 1 span 2 4 2 3 cover 4 0... quant 1 2 3 span 0 2 4 1 span 2 4 2 3 cover 4 0... 5, XC4062 Xilinx Bitstreams 8 minutes 10X Faster

7. Baseline -- ‘96 PPC PowerPC SLAAC SLAAC SAR/ATR Roadmap - 500:1 Acceleration vs. ‘96 Baseline 50x 25x 10x 8x 10x Homogeneous ACS FPGAs upgrade to latest technology. Heterogeneous ACS (e.g. memory on chip) Hybrid ACS (e.g. RISC core, RTR) 1 10 100 1000 9697 98 9900 01 Year Performance Moore’s Law Arch. Advantage Goal Fine-grain parallelism Fine-grain control Dynamic load balance Precision management Skip “0” Early outs Initial Arch. Advantage Fine-grain parallelism Coarse-grain control ACS SLAAC BYU ACS FOA Performance (10x PowerPC) (morphology portion)

8. Superquant •Adaptive image quantization (AIQ). –Histogram generation and search. –First stage of the FOA algorithm. –Memory-bandwidth limited, not compute-bound. •Implementation –Exploits distributed memories. –Fully parameterizable (uses.def file). • Status: –Histogram processors have been designed and verified. –Projected pixel rates: »estimated, Xilinx 4K: 6-7 Mpixel (30 MHz). June 99. »estimated, Xilinx Virtex: 12-14 Mpixel (60 MHz). ?

9. FOA Future Vision (Virtex) Superquant Binary Morphology Binary Morphology Image Data Output +3 Chip Solution +1 board +30 Mpixel

10. Future Issues •Release source of BYU-FOA compiler to Sandia. •AIQ (adaptive image quantization) aka Superquant –Initial designs are complete. •CDI –Studying specification. •Study advantages of Xilinx Virtex. –Faster clocks, fewer chips, lower cost, yada, yada, yada...