IMPLEMENTATION OF MIPS 64 WITH VERILOG HARDWARE DESIGN LANGUAGE BY PRAMOD MENON CET520 S’03

GOALS FOR THE PROJECT To implement the MIPS 64 architecture with Verilog hardware design language. Follow the ASIC design flow for implementation Understand Verilog coding styles and optimize code design Using Verilog implement the single cycle Implementation scheme Implement Pipelined scheme using Verilog Improve Pipelining by adding forwarding unit and Hazard detection to prevent hazards Use a Branch optimization technique in the pipeline with Verilog Compare and draw conclusions between the single cycle, Pipeline and pipeline with branch optimization based on parameters obtained on synthesis

ASIC DESIGN FLOW 1. Design Specification 2. Design Partition 3. Design Entry Verilog Behavioral Modeling 4. Simulation/Functional Verification 5. Design Integration and Verification 7. Synthesize and Map Gate-Level Netlist 6. Presynthesis Sign-Off 8. Post-synthesis Design Validation 9. Post-synthesis Timing Validation 10. Test Generation and Fault Simulation 11. Cell Placement, Scan Chain & Clock Tree Insertion. Cell Routing 12. Verify Physical and Electrical Design Rules 13. Extract Parasitic 14. Design Sign-Off Production ready Masks

VERILOG INTRODUCTION Verilog is a Hardware Description Language (HDL). 1980s,A company called Gateway Design Automation developed a logic simulator, Verilog-XL, and with it a hardware description language. Cadence Design Systems acquired Gateway in 1989, and with it the rights to the language and the simulator. In 1990, Cadence put the language (but not the simulator) into the public domain, with the intention that it should become a standard, non-proprietary language. The Verilog HDL is now maintained by a non-profit making organization, Open Verilog International (OVI). OVI had the task of taking the language through the IEEE standardization procedure. A Hardware Description Language is a language used to describe a digital system or a component Simulation of designs before it goes to fabrication. Different Levels – Switch, Gate, RTL Why HDL? Millions of Transistors Explore Architectural alternatives Take care of bottlenecks

BASIC VERILOG A chip contain many modules A module is a basic block A module uses predefined cells (Mux, Adder) Everything is based on primitives (e.g. NAND) Chip Modules Cells Primitives

VERILOG LANGUAGE Module ( ); endmodule endmodule Module_tb( ); Initialbegin Clk= 1’b0; #50 clk = ~clk; //clock toggles end The is an identifier that uniquely names the module. The is a list of input, in-out and output ports which are used to connect to other modules. The section specifies data objects as registers, memories and wires as wells as procedural constructs such as functions and tasks.

Single Cycle

PIPELINED

PIPELINED WITH FORWARDING

PIPELINED WITH HAZARD UNIT

PIPELINE WITH BRANCH

PARAMETERS COMPARED CELLSAREA DYNAMIC POWER SLACKCLOCK

SYNTHESIS RESULTS SINGLEPIPELINE PIPELINE FWD PIPELINE HAZARD UNIT PIPELINE WITH BRANCH CELLS AREA DYNAMIC POWER 1.78mW2.39mW3.53mW3.9mW 4.8 mW SLACK CLOCK60ns32ns54ns72ns62

CONCLUSION Area Tradeoffs Power dissipated Clock Cycles