1. ECE 2372 Modern Digital System Design
Section 7.1
Introduction to
Hardware Descriptive Language

2. Introduction to HDL
A Hardware Descriptive Language (HDL) allows the digital designer to describe the behavior of a circuit using a high-level computer language.
The description may take the form of an algorithm, logic equations or truth table.
This high-level description of the digital system may be compiled into a file that is used to program a Programmable Logic Device, or may be processed by a Silicon Compiler to produce the masks used to create integrated circuits.

3. Introduction to HDL One HDL is Verilog.
Xilinx features a Verilog editor, synthesizer and simulator.

4. HDL Design Process

5. Verilog File Structure
The basic unit of Verilog Code is called a Module.
A Verilog module has the following format.

6. Verilog File Structure
The keywords are module and endmodule.
The modulename identifies the module and may include any letters, numbers the $ sign and the _ underscore.
Verilog identifiers are case sensitive..
The modulename is followed by a list of input and output ports.

7. Verilog File Structure
Parameters are used to define numerical constants.
These constants are often used to make designs more general and flexible.
The numerical constants may be decimal, hexadecimal, octal or binary. Numbers are 32 bit unless otherwise specified.

8. Verilog File Structure
Some valid numerical constants are:

9. Verilog File Structure
The port declarations are used to describe the input and output ports.
The input ports are declared with the keywords:

10. Verilog File Structure
Bits are individually referenced by B[3], B[2], B[1] and B[0].
The most significant bit is listed first.

11. Verilog File Structure
The port declarations are used to describe the input and output ports.
The output ports are declared with the keywords:

12. Verilog File Structure

13. Verilog File Structure
The wire declarations define the connections between logic gates and sub-modules within a module.
These correspond to physical conductors in a logic circuit.
A wire variable type has no memory and cannot be used to store a value.
A wire must be connected to the output of a gate or must be assigned a value.

14. Verilog File Structure

15. Verilog File Structure

16. Verilog File Structure
The reg declarations are used to define registers.
These are variables that have memory and may be used to store a value.
These are in effect variables that retain logical values during a Verilog process.
A register may also be assigned to output ports.

17. Verilog File Structure

18. Verilog File Structure
The submodule instantiations are where logic gates and other Verilog modules may be incorporated into a module.

19. Verilog File Structure
The description of the Verilog module follows.
A Module may be defined with Structural Descriptions or Behavioral Descriptions.
The module is closed with the endmodule keyword.
The structure of a Verilog file is demonstrated in the following example of a full adder.
The purpose of each line keyword and operator is explained in the comments.

20. Verilog File Structure

21. Verilog File Structure

22. Verilog File Structure
This is a Data Flow Description of a full adder that uses the assign keyword to make a continuous assignment to the output ports.
These assignments may use the logical operators.
Operators (in order of precedence)
~ NOT
& AND
| OR
^ XOR
^~ XNOR

23. Verilog File Structure

25. Verilog File Structure
The wire keyword is used to define three intermediate terms used in the module.
Each of the gates is defined individually.
The gate definitions are of the form
gate_type gate_name1(output, inputs), gate_name2(output, inputs);
The Gate Type may be any of the standard logic gates.

26. Verilog File Structure
Gate Definitions:
and gate_name(output, inputs)
nand gate_name(output, inputs)
or gate_name(output, inputs)
nor gate_name(output, inputs)
xor gate_name(output, inputs)
xnor gate_name(output, inputs)
not gate_name(output, input)
buf gate_name(output, input)

27. Verilog File Structure
This for is a Verilog Structural Description.
The gate_name may be any valid Verilog name.
Gate names should be chosen to be descriptive and to distinguish the gates.
The gates are assumed to be single output, with any integer number of inputs greater than one.
The same full adder may be described with a Functional Description that implements the mathematical operation as follows.

28. Verilog File Structure

29. Verilog File Structure
The brackets {} indicate a concatenation of the two single bit variables.
The expression uses the Binary Arithmetic Addition operator, not the Boolean Or operator. .
A module may be called from within a module.
Consider the 4-bit ripple adder made up of 4 full adders as follows:

30. Verilog File Structure
The full adder can be designed once, and then called (as if it were a sub-routine) 4 times in creating a 4-bit adder.

31. Verilog File Structure

32. Verilog File Structure

33. Verilog File Structure

34. Verilog File Structure
The sub-module FullAdder is invoked in 4 instantiations.
A unique name is given to each of the instantiations.
The same 4-bit adder may be described using the functional description:

35. Verilog File Structure

36. Conditional Operator
The conditional operator ( ? : ) evaluates an expression and returns a value if the expression is true.
The conditional operator is used in assign statements as follows:

37. Conditional Operator
The conditional operator is demonstrated in the following example (x assigns an “unknown”):

38. Conditional Operator
Conditional operations may be nested as demonstrated in the following example:

39. Sequential Logic Circuits
Sequential logical circuits are described using Procedural Descriptions.
The two types of processes are initial and always.
The initial process is executed once when the module is executed.
The always process is executed continuously when the module executed.
The process defined by the statements between the begin and end keywords.

40. Sequential Logic Circuits
An initial process is illustrated by the following code fragment.

41. Sequential Logic Circuits
An always process is illustrated by the following code fragment.

42. Sequential Logic Circuits
The always procedure must be triggered by an event.
This event may be a change in the value of a variable as illustrated in the code fragment below.

43. Sequential Logic Circuits
This type of event-expression is typically used to synthesize asynchronous sequential circuits.

44. Sequential Logic Circuits
Synchronous sequential circuits are typically triggered by the rising or falling edges of signals.
This is illustrated in the code fragment below.

45. Conditional Statements
A conditional procedure may be written using if-else statements as follows

46. Conditional Statements
Multiple conditions may be included with the form:

47. Conditional Statements
An alternative conditional process may be written using case statements.

48. Conditional Statements
Case statements may be combined with if-else statements:

50. Conditional Statements
A procedure may be initiated by a clock or an asynchronous preload condition.

51. Blocking Assignments
Consider the fragment of Verilog code listed below. Assuming that the variables A, B and C have some initial value.

52. Blocking Assignments
A the end of the end of the process, both B and C have the value originally assigned to A.
The assignments have been made sequentially.

53. Non-blocking Assignments
Consider the fragment of Verilog code listed below. Assuming that the variables A, B and C have some initial value.

54. Non-blocking Assignments
At the end of the end of the process, B has the value originally assigned to A. The variable C has the value originally assigned to B.
The assignments have been made concurrently.

55. JK Flip Flop
Additional keywords and operators are demonstrated in the following Verilog file. This module implements a JK Flip Flop.

57. Operators
In order of precedence:

58. Sequence Recognizer for 1101
State Transition Table:

65. 4-bit Storage Register

67. 4-bit Shift Register with Asynchronous Clear

69. 4-bit Binary Counter with Synchronous Clear

71. 16 x 8-bit synchronous RAM

72. Dout7
Dout6
Dout5
Dout4
ADDR3
Dout3
ADDR2
Dout2
ADDR1
Dout1
ADDR0
Dout0
Dout
Din7
Din6
Din5
RamData15
Din4
RamData14
Din3
Din2
Din1
Din0
RamData0
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