1. O VERVIEW OF DIGITAL SYSTEMS Hardware Description Language 1

2. D EFINITION A hardware description language is the language that describes the hardware of digital systems in textual form and resembles a programming language, but specifically oriented to describing hardware structures and behavior. 2

3. H ARDWARE D ESCRIPTION L ANGUAGE (HDL) Basic idea is a programming language to describe hardware Initial purpose was to allow abstract design and simulation Design could be verified then implemented in hardware Now Synthesis tools allow direct implementation from HDL code. Large improvement in designer productivity 3

4. H ARDWARE D ESCRIPTION L ANGUAGE (HDL) HDL allows write-run-debug cycle for hardware development. Similar to programming software Much, much faster than design-implement-debug Combined with modern Field Programmable Gate Array chips large complex circuits (>100000s of gates) can be implemented. 4

5. Advantages of HDL 5

6. HDL S There are many different HDLs Verilog HDL ABEL VHDL VHDL is the most common Large standard developed by US DoD VHDL = VHSIC HDL VHSIC = Very High Speed Integrated Circuit Verilog HDL is second most common Easier to use in many ways = better for teaching C - like syntax 6

7. S TANDARD HDL SUPPORTED BY IEEE VHDL – (Very high speed integrated circuit Hardware Description Language) ) became IEEE standard 1076 in 1987. It was updated in 1993 and is known today as "IEEE standard 1076 1993 - a Department of Defense mandated language that was initially used by defense contractors, but is now used commercially and in research universities. - a Department of Defense mandated language that was initially used by defense contractors, but is now used commercially and in research universities. 7

8. S TANDARD HDL SUPPORTED BY IEEE Verilog – ". The Verilog hardware description language has been used far longer than VHDL and has been used extensively since it was launched by Gateway in 1983. Cadence bought Gateway in 1989 and opened Verilog to the public domain in 1990. It became IEEE standard 1364 in December 1995. - a proprietary HDL promoted by a company called Cadence Data systems, but Cadence transferred control of Verilog to a consortium of companies and universities known as Open Verilog International (OVI). - a proprietary HDL promoted by a company called Cadence Data systems, but Cadence transferred control of Verilog to a consortium of companies and universities known as Open Verilog International (OVI). 8

9. A T ALE OF T WO HDL S VHDL Verilog 9

10. D IGITAL D ESIGN USING V ERILOG 10

11. H ISTORY Paper or breadboard Gate level 11

12. Too low-level for initial functional specification Early high-level design exploration Abstract behavioral model 12

13. V ERILOG HDL Verilog constructs are use defined keywords Examples: and, or, wire, input output One important construct is the module Modules have inputs and outputs Modules can be built up of Verilog primatives or of user defined submodules. 13

14. We will use Verilog… 14

15. V ERILOG C APABILITIES Primitive logic gates, such as and, or and nand, are built-in into the language. It has built-in logic functions such as & (bitwise-and) and | (bitwise-or). Flexibility of creating a user-defined primitive (UDP). Such a primitive could either be a combinational logic primitive or a sequential logic primitive. Switch-level modeling primitive gates, such as pmos and nmos, are also built-in into the language. 15

16. V ERILOG C APABILITIES Explicit language constructs are provided for specifying pin-to-pin delays, path delays and timing checks of a design. A design can be modeled in three different styles or in a mixed style. These styles are: behavioral style- modeled using procedural constructs; dataflow style – modeled using continuous assignments; and structural style- modeled using gate and module instantiations. 16

17. V ERILOG C APABILITIES There are two data types in Verilog HDL; the net data type and the register data type. Hierarchical designs can be described, up to any level, using the module instantiation construct. A design can be of arbitrary size. Verilog HDL is non-proprietary and is an IEEE standard. It is human and machine readable. Thus, it can be used as an exchange language between tools and designers. 17

18. V ERILOG C APABILITIES The capabilities of the Verilog HDL language can be further extended by using the programming language interface (PLI) mechanism. A design can be described in a wide range of levels, ranging from switch-level, gate-level, register-transfer-level (RTL) to algorithmic- level, including process and queuing-level. A design can be modeled entirely at the switch-level using the built-in switch-level primitives. 18

19. V ERILOG C APABILITIES switch algorithm gate switch RTL gate Mixed-Level Modeling 19

20. V ERILOG C APABILITIES The same single language can be used to generate stimulus for the design and for specifying test constraints, such as specifying the values of inputs. Verilog HDL can be used to perform response monitoring of the design under test. High-level programming language constructs such as conditionals, case statements, and loops are available in the language. 20

21. Notion of concurrency and time can be explicitly modeled. Powerful file read and write capabilities are provided. The language is non-deterministic under certain situations. Verilog Capabilities 21

22. Q UICK T UTORIAL OF THE L ANGUAGE Module. The basic unit of description and is the building block in Verilog. It describes the functionality or structure of a design and also describes the ports through which it communicates externally with other modules. 22

23. E XAMPLE : S IMPLE C IRCUIT HDL module smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e; and g1(e,A,B); not g2(y, C); or g3(x,e,y); endmodule 23

24. B ASIC SYNTAX OF A MODULE module module_name (port_list); Declarations: reg,wire,parameter, reg,wire,parameter, input,output,inout, input,output,inout, function, task,… function, task,… Statements: Statements: Initial statement Initial statement Always statement Always statement Module instantiation Gate instantiation UDP instantiation Continuous assignment endmodule 24

25. E XAMPLE 25

26. F ULL ADDER 26

27. F ULL ADDER 27

28. F ULL ADDER 28

29. T HANK Y OU ! 29