1. KARTHIK.S Lecturer/ECE S.N.G.C.E
VERILOG HDL
IEEE STD 1364
" It may not take more than one week, if you happen to know at least one programming language".
KARTHIK.S Lecturer/ECE S.N.G.C.E
Karthik.S S.N.G.C.E

2. CONTENTS Introduction. History of Verilog. Design and Tool Flow.
What is Verilog HDL.
Verilog HDL language elements.
My First Program in Verilog.
Verilog data flow Modeling.
Structural Modeling
Verilog behavioral modeling.
Procedural Timing Controls.
Tasks and Function.
System Tasks and Functions.
Art of writing test benches.
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3. Introduction. Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL).
A hardware description Language is a language used to describe a digital system, for example, a microprocessor or a memory or a simple flip-flop.
This just means that, by using a HDL one can describe any hardware (digital ) at any level.
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4. HISTORY
Verilog was started initially as a proprietary hardware modeling language by Gateway Design Automation Inc. around 1984.
Verilog simulator was first used beginning in 1985 and was extended substantially through 1987.The implementation was the Verilog simulator sold by Gateway.
After many years, new features have been added to Verilog, and new version is
called Verilog 2001.
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5. INTRODUCTION
Typical Design flow
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6. SPECIFICATION HIGH LEVEL DESIGN
This is the stage at which we define what are the important parameters of the system/design that you are planning to design.
HIGH LEVEL DESIGN
This is the stage at which you define various blocks in the design and how they communicate.
Example: Microprocessor
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7. LOW LEVEL DESIGN RTL CODING
Low level design or Micro design is the phase in which, designer describes how each block is implemented.
RTL CODING
In RTL coding, Micro Design is converted into Verilog/VHDL code, using synthesizable constructs of the language.
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8. SIMULATION
Simulation is the process of verifying the functional characteristics of models
We use simulators to simulate the Hardware models.
To test if the RTL code meets the functional requirements of the specification, see if all the RTL blocks are functionally correct.
SYNTHESIS
Simulation is the process in which the synthesis tools takes the RTL code to the target technology.
It maps RTL codes to the gates & primitives and do minimal amount of timing analysis.
Example: Xillinx ISE, QuatrusII. CONTENTS
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9. MY Ist PROGRAM
If we refer to any text book on programming language it starts with “HELLO WORLD” program. I start with “WELCOME” program.
// Design name: Welcome to SNGCE
// File name: welcome.v
// Coder: Karthik.S
module welcome;
initial begin
$display (“welcome to SNGCE”);
end
endmodule
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10. VERILOG HDL Single language for design & Simulation.
Three types of modeling
1. DATAFLOW
2. STRUCTURAL
3. BEHAVIORAL
Built-in primitives & logic functions
Built-in data types
User defined primitives.
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11. BASIC UNIT-MODULE Modules communicates externally with input & output.
A module can be instantiated into other module.
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12. EXAMPLE
One can describe a simple Flip flop as that in above figure as well as one can describe a complicated designs having 1 million gates. CONTENTS
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13. VERILOG SYNTAX
Verilog is free-format language. White space can be used freely.
Verilog is CASE Sensitive
User provided names are called identifiers and should start with a “letter” or “_” example: CONUT_1
Predefined identifiers are called keywords. All keywords are lower case. Example: assign, module, begin, end, etc.,
Comments- two forms: /* first form*/ & // second form
Value set: 1(high), 0(low), X(unknown), Z(high impedance).
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14. NUMBER REPRESENTATION
<size><base format><number>
Examples:
8'h FF // hex number
8‘d65 // octal number
4'b11 // 4-bit binary number 0011
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15. DATA TYPES Represent abstract data values.
NETS:
Connects b/w structural elements.
Values comes from it’s drivers
Can be used in data flow & structural modeling
Default value is Z
Example: wire
REGISTERS:
Represent abstract data values.
Values in a register is saved until new value is stored.
Default value is X
Example: reg
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16. DATA FLOW
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17. INTRODUCTION
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18. DELAYS
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19. OPERATORS
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20. EXAMPLE
module half_adder (sum,cout,a,b,cin); input a, b, cin; output sum, cout; assign sum = a ^ b;// assignment should be done //with <= sign. assign cout = a & b; endmodule
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21. EXAMPLE 2 2X1 MUX
module mux_2 ( y, s, a, b); input s, a, b; output y; assign y = s?a : b; // if s=0 y=a else y=b endmodule
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22. STRUCTURAL
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23. GATE LEVEL MODELING
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24. 4X1 MUX
module mux_4 (y,s0,s1,a,b,c,d); input a,b,c,d,s0,s1; output y; not n1(s0bar,s0); // gate instantiation starts here not n2(s1bar,s1); and a1(t0,s0bar,s1bar,a); and a1(t1,s0bar,s1,b); and a1(t2,s0,s1bar,c); and a1(t3,s0,s1,d); or o1(y,t0,t1,t2,t3); endmodule
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25. UER DEFINED PRIMITIVES
Module instantiation can be done i.e. module within a module.
A 4-bit RCA can be designed using 4 full adders.
First a full adder is designed and it is called or instantiated in the RCA
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26. EXAMPLE
module RCA ( sum, cout, a, b, cin); input [3:0] a, b; output[3:0] sum; input cin; output cout; module fa ( s, cy, x, y, c); input x,y,c; output s, cy; assign s<= x^y^c; assign cy<= (x&y) | (y&c) | (c&x); endmodule
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27. Karthik.S S.N.G.C.E
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