George Mason University ECE 448 – FPGA and ASIC Design with VHDL Practice final exam Solutions ECE 448 Review Session

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 1

3ECE 448 – FPGA and ASIC Design with VHDL High-Level Languages C-Based System level languages Commercial SystemC -- The Open SystemC Initiative Handel C -- Celoxica Ltd. Impulse C -- Impulse Accelerated Technologies Research Streams-C -- Los Alamos National Laboratory SA-C -- Colorado State University, University of California, Riverside, Khoral Research, Inc. SpecC – University of California, Irvine and SpecC Technology Open Consortium

4ECE 448 – FPGA and ASIC Design with VHDL Other High-Level Design Flows Matlab-based AccelChip DSP Synthesis -- AccelChip System Generator for DSP -- Xilinx GUI Data-Flow based Corefire -- Annapolis Microsystems Java-based Commercial Forge -- Xilinx Research JHDL – Brigham Young University

5ECE 448 – FPGA and ASIC Design with VHDL Two major high-level language (HLL) programming models SRC 6 & SRC 7 from SRC Computers Cray XD1 from from Cray SGI Altix from SGI SRC MAP C programming model Mitrion-C programming model

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 2

7ECE 448 – FPGA and ASIC Design with VHDL Most advanced reconfigurable computing machines currently on the market Machine Released SRC 6 from SRC Computers Cray XD1 from from Cray SGI Altix from SGI SRC 7 from SRC Computers, Inc,

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 3

9ECE 448 – FPGA and ASIC Design with VHDL Introduction CAD tools provide several advantages Ability to evaluate complex conditions in which solving one problem creates other problems Use analytical methods to assess the cost of a decision Use synthesis methods to help provide a solution Allows the process of proposing and analyzing solutions to occur at the same time Electronic Design Automation Using CAD tools to create complex electronic designs (ECAD) Several companies who specialize in EDA Synopsys® Cadence® Design Systems Magma® Design Automation Inc. Mentor Graphics® CAD Tools Allow Large Problems to be Solved

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 4

11ECE 448 – FPGA and ASIC Design with VHDL Wireload model basics (2)

12ECE 448 – FPGA and ASIC Design with VHDL Wireload model basics (1)

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 5

14ECE 448 – FPGA and ASIC Design with VHDL Physical Verification Checks the design for fabrication feasibility and physical defects that could result in the design to not function properly 3 checks (DRC, ERC, and LVS) Design Rule Checks (DRC) Verifies that design does not violate any fabrication rules associated with the target process technology (metal width/space, antenna ratio, etc) Electrical Rules Checks (ERC) Verifies that there are no short or open circuits with power and ground as well as resistors/capacitors/transistors with floating nodes (part of LVS) Layout Versus Schematic (LVS) Final physical design matches the logical (schematic) version in terms of correct connectivity and number of electrical devices Hercules™ is the Sign-Off Tool for Physical Verification

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 6

16ECE 448 – FPGA and ASIC Design with VHDL Technology File Layer and via Definitions Process design rules (Minimum metal widths and spacing) Resistance / Capacitance parasitic models Units (Time / Capacitance / Distance) GUI display information (Colors and fill template for layers) This file is stored in the design library (Common Database)

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 7

18ECE 448 – FPGA and ASIC Design with VHDL Xilinx Spartan-3 Block RAM Port Aspect Ratios

19ECE 448 – FPGA and ASIC Design with VHDL

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 8

21ECE 448 – FPGA and ASIC Design with VHDL

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 9

23ECE 448 – FPGA and ASIC Design with VHDL

24ECE 448 – FPGA and ASIC Design with VHDL SONET Virtex-4 RocketIO™ Full-duplex serial transceiver blocks with integrated SERDES and Clock and Data Recovery 622 Mbps to >10 Gbps I/O Widest speed range Compatible with Virtex-II Pro Supports chip-to-chip, backplane, chip-to-optics Multi-Gigabit Transceivers

25ECE 448 – FPGA and ASIC Design with VHDL

26ECE 448 – FPGA and ASIC Design with VHDL Microprocessor & Ethernet PowerPC405EMAC EMAC Hard EMACs Ethernet Media Access Controller EMAC with PowerPC PowerPC runs Protocol Stacks EMAC used to debug and control PPC or PPC to configure and control the EMAC EMAC without PowerPC Any application with control state machine or soft processor in the FPGA fabric Two EMACs per PowerPC Redundancy Bridging Hard Ethernet Controller saves 6000 slices

27ECE 448 – FPGA and ASIC Design with VHDL Dedicated Circuits in FPGAs “Hard” cores offer density, speed, lower power Equal to 90-nm ASICs, but far less expensive Expandable, pipelined Multiplier/Accumulator Dual-ported BlockRAM with FIFO controller ChipSynch I/O serializer/ deserializer + IDELAY Multi-Gigabit transceivers, 0.6 to 11 Gbps PowerPC µProcessor and Ethernet controller Dedicated circuits provide a big performance boost

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 10

29ECE 448 – FPGA and ASIC Design with VHDL

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 11

31ECE 448 – FPGA and ASIC Design with VHDL Customary schematic for a PLA f 1 P 1 P 2 f 2 x 1 x 2 x 3 OR plane AND plane P 3 P 4

32ECE 448 – FPGA and ASIC Design with VHDL Programmable Array Logic f 1 P 1 P 2 f 2 x 1 x 2 x 3 AND plane P 3 P 4

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 12

34ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( A generic structure of CPLD (Complex Programmable Logic Device)

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 13

36ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Frequency Synthesis

37ECE 448 – FPGA and ASIC Design with VHDL DLL vs PLL DLL is a rugged & reliable digital circuit PLL is a more sensitive linear circuit Voltage-controlled Oscillator needs clean supply DLL has unavoidable jitter PLL can reduce jitter, But only if carefully designed and supplied Frequency Multiplication is easier with PLL PLL supply filtering can be very difficult

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 14

39ECE 448 – FPGA and ASIC Design with VHDL Reconfiguration Interfaces in Xilinx FPGAs SelectMap (8 bits Parallel) JTAG Internal Port ICAP (Virtex-II)

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 15

41ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 16

43ECE 448 – FPGA and ASIC Design with VHDL Procedures – basic features Procedures do not return a value are called using formal and actual parameters the same way as components may modify parameters passed to them each parameter must have a mode: IN, OUT, INOUT parameters can be constants (including generics), signals (including ports), and variables; the default for inputs (mode in) is a constant, the default for outputs (modes out and inout) is a variable when passing parameters, range specification should be included (for example RANGE for INTEGERS, and TO/DOWNTO for STD_LOGIC_VECTOR) Procedure calls are statements on their own

44ECE 448 – FPGA and ASIC Design with VHDL Functions – basic features Functions always return a single value as a result are called using formal and actual parameters the same way as components never modify parameters passed to them parameters can only be constants (including generics) and signals (including ports); variables are not allowed; the default is a CONSTANT when passing parameters, no range specification should be included (for example no RANGE for INTEGERS, or TO/DOWNTO for STD_LOGIC_VECTOR) are always used in some expression, and not called on their own

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 17

46ECE 448 – FPGA and ASIC Design with VHDL Typical locations of subprograms FUNCTION / PROCEDURE PACKAGE PACKAGE BODY LIBRARY global ARCHITECTURE Declarative part local for a given architecture ENTITY local for all architectures of a given entity

47ECE 448 – FPGA and ASIC Design with VHDL Package containing a function (1) LIBRARY IEEE; USE IEEE.std_logic_1164.all; PACKAGE specialFunctions IS FUNCTION Pow( SIGNAL N: INTEGER; Exp : INTEGER) RETURN INTEGER; END specialFunctions

48ECE 448 – FPGA and ASIC Design with VHDL Package containing a function (2) PACKAGE BODY specialFunctions IS FUNCTION Pow(SIGNAL N: INTEGER; Exp : INTEGER) RETURN INTEGER IS VARIABLE Result : INTEGER := 1; BEGIN FOR i IN 1 TO Exp LOOP Result := Result * N; END LOOP; RETURN( Result ); END Pow; END specialFunctions

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Part I Problem 18

50ECE 448 – FPGA and ASIC Design with VHDL Operator overloading Operator overloading allows different argument types for a given operation (function) The VHDL tools resolve which of these functions to select based on the types of the inputs This selection is transparent to the user as long as the function has been defined for the given argument types.

51ECE 448 – FPGA and ASIC Design with VHDL Different declarations for the same operator - Example Declarations in the package ieee.std_logic_unsigned: function “+” ( L: std_logic_vector; R:std_logic_vector) return std_logic_vector; function “+” ( L: std_logic_vector; R: integer) return std_logic_vector; function “+” ( L: std_logic_vector; R:std_logic) return std_logic_vector;