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George Mason University FPGA Memories ECE 448 Lecture 13.

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Presentation on theme: "George Mason University FPGA Memories ECE 448 Lecture 13."— Presentation transcript:

1 George Mason University FPGA Memories ECE 448 Lecture 13

2 2 Recommended reading Spartan-6 FPGA Block RAM Resources: User Guide Google search: UG383 Spartan-6 FPGA Configurable Logic Block: User Guide Google search: UG384 Xilinx FPGA Embedded Memory Advantages: White Paper Google search: WP360

3 3 Recommended reading XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques Sections: RAM HDL Coding Techniques ROM HDL Coding Techniques ISE In-Depth Tutorial, Section: Creating a CORE Generator Tool Module

4 4 Memory Types

5 5 Memory RAMROM Single portDual port With asynchronous read With synchronous read Memory

6 6 Memory Types specific to Xilinx FPGAs Memory Distributed (MLUT-based) Block RAM-based (BRAM-based) InferredInstantiated Memory Manually Using CORE Generator

7 7 FPGA Distributed Memory

8 8 Location of Distributed RAM Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) DSP units RAM blocks Logic resources (CLB slices)

9 9 Three Different Types of Slices 50%25%

10 10 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Spartan-6 Multipurpose LUT (MLUT) 64 x 1 ROM (logic) 64 x 1 RAM 32-bit SR

11 11 Single-port 64 x 1-bit RAM

12 12 Memories Built of Neighboring MLUTs Single-port 128 x 1-bit RAM: RAM128x1S Dual-port 64 x 1-bit RAM : RAM64x1D Memories built of 2 MLUTs: Memories built of 4 MLUTs: Single-port 256 x 1-bit RAM: RAM256x1S Dual-port 128 x 1-bit RAM: RAM128x1D Quad-port 64 x 1-bit RAM:RAM64x1Q Simple-dual-port 64 x 3-bit RAM:RAM64x3SDP (one address for read, one address for write)

13 13 Dual-port 64 x 1 RAM Dual-port 64 x 1-bit RAM : 64x1D Single-port 128 x 1-bit RAM: 128x1S

14 14 Total Size of Distributed RAM

15 15 FPGA Block RAM

16 16 Location of Block RAMs Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) DSP units RAM blocks Logic resources (CLB slices)

17 17 Spartan-6 Block RAM Amounts

18 18 Block RAM can have various configurations (port aspect ratios) 0 16,383 1 4,095 4 0 8,191 2 0 2047 8+1 0 1023 16+2 0 16k x 1 8k x 2 4k x 4 2k x (8+1) 1024 x (16+2)

19 19

20 20

21 21 Block RAM Port Aspect Ratios

22 22 Block RAM Interface

23 23 Block RAM Ports

24 24 Block RAM Waveforms – READ_FIRST mode

25 25 Block RAM Waveforms – WRITE_FIRST mode

26 26 Block RAM Waveforms – NO_CHANGE mode

27 27 Features of Block RAMs in Spartan-6 FPGAs

28 28 Inference vs. Instantiation

29 29

30 30 Using CORE Generator

31 31 CORE Generator

32 32 CORE Generator

33 33 Generic Inferred ROM

34 34 Distributed ROM with asynchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; Entity ROM is generic ( w : integer := 12; -- number of bits per ROM word r : integer := 3); -- 2^r = number of words in ROM port (addr : in std_logic_vector(r-1 downto 0); dout : out std_logic_vector(w-1 downto 0)); end ROM;

35 35 Distributed ROM with asynchronous read architecture behavioral of rominfr is type rom_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := ("000011000100", "010011010010", "010011011011", "011011000010", "000011110001", "011111010110", "010011010000", "111110011111"); begin dout <= ROM_array(conv_integer(unsigned(addr))); end behavioral;

36 36 Distributed ROM with asynchronous read architecture behavioral of rominfr is type rom_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := ("0C4", "4D2", "4DB", "6C2", "0F1", "7D6", "4D0", "F9F"); begin dout <= ROM_array(conv_integer(unsigned(addr))); end behavioral;

37 37 Generic Inferred RAM

38 38 Distributed versus Block RAM Inference Examples: 1.Distributed single-port RAM with asynchronous read 2.Distributed dual-port RAM with asynchronous read 1.Block RAM with synchronous read (no version with asynchronous read!) More excellent RAM examples from XST Coding Guidelines.

39 39 Distributed single-port RAM with asynchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr;

40 40 Distributed single-port RAM with asynchronous read architecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end process; do <= RAM(conv_integer(unsigned(a))); end behavioral;

41 41 Distributed dual-port RAM with asynchronous read library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); dpra : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); spo : out std_logic_vector(w-1 downto 0); dpo : out std_logic_vector(w-1 downto 0)); end raminfr;

42 42 Distributed dual-port RAM with asynchronous read architecture syn of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end process; spo <= RAM(conv_integer(unsigned(a))); dpo <= RAM(conv_integer(unsigned(dpra))); end syn;

43 43 Block RAM Waveforms – READ_FIRST mode

44 44 Block RAM with synchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 9); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr;

45 45 Block RAM with synchronous read Read-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then do <= RAM(conv_integer(unsigned(addr))); if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di; end if; end process; end behavioral;

46 46 Block RAM Waveforms – WRITE_FIRST mode

47 47 Block RAM with synchronous read Write-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di; do <= di; else do <= RAM(conv_integer(unsigned(addr))); end if; end process; end behavioral;

48 48 Block RAM Waveforms – NO_CHANGE mode

49 49 Block RAM with synchronous read No-Change Mode - cont'd architecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di; else do <= RAM(conv_integer(unsigned(addr))); end if; end process; end behavioral;

50 50 Criteria for Implementing Inferred RAM in BRAMs

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