Programmable Logic Devices (PLDs) 25-Apr-17 Programmable Logic Devices (PLDs) Wannachai wannasaeade Department of Computer Education KMUTNB. Chapter 6-i: Programmable Logic Devices (Sections 6.5 -- 6-8)

Overview Three-State Buffers Programmable Logic Technologies Read-Only Memory (ROM) Simple Programmable Logic Device Programmable Logic Arrays (PLA) Programmable Array Logic (PAL) Gate Array Logic (GAL) Complex Programmable Logic (CPLD) Field Programmable Gate Array (FPGA)

Three-State Buffers Buffer output has 3 states: 0, 1, Z Z stands for High-Impedance  Open circuit EN = 0  out = Z (open circuit) EN = 1  out = in (regular buffer) EN EN in out X Z 1 in out

Three-state buffer(BUF)/inverter(INV) symbols EN EN in out in out 3-state BUF, EN high 3-state INV, EN high EN EN in out in out 3-state BUF, EN low 3-state INV, EN low

Multiplexed output lines using three-state buffers Assume an output line that can receive data from either a system (circuit) A or a system B. A If A = B  out = A = B If A  B  a large enough current can be created, that causes excessive heating and could damage the circuit. out B wired logic

Multiplexed output lines using three-state buffers (cont.) Solution: A B S out 1 S A B ENA ENB out 1 A B out ENA ENB S A B

Programmable Logic Devices (PLDs) Standard logic devices that can be programmed to implement any combinational logic circuit. Standard  of regular structure Programmed  refers to a hardware process used to specify the logic that a PLD implements

Gate Symbols One major difference! . . . . . . Conventional AND gate symbol Array Logic AND gate symbol One major difference! a b c F = 0 a F b c F = a.c F = a.b.c

Read-Only Memory (ROM) Stores binary information permanently Non-Volatile (info is kept even when power is turned off) k inputs = specify the # of addresses available n outputs = specify the size of data ROM 2k x n k n Block Diagram

Read-Only Memory (cont.) Address 8x4 ROM Example: k=3, n=4 There are 23=8 available addresses 4-bits are stored in each address 1 2 3 4 5 6 7 3 4

ROM construction: Example of an 25x8 ROM Use a 5-to-32 decoder to generate the 32 addresses. Use 8 OR gates, each can be programmed to be driven by any of the decoder outputs. Programmable logic. # of interconnections is 25x8

Programming the ROM, i.e. load desired data at specified addresses (in decimal) 1 2 3 28 29 30 31 ROM addresses ROM data

Programming the ROM (cont.) Example: Let I0I1I3I4 = 00010 (address 2). Then, output 2 of the decoder will be 1, the remaining outputs will be 0, and ROM output becomes A7A6A5A4A3A2A1A0 = 11000101.

ROM-based circuit implementation Given a 2kxn ROM, we can implement ANY combinational circuit with at most k inputs and at most n outputs. Why? k-to-2k decoder will generate all 2k possible minterms Each of the OR gates must implement a m() Each m() can be programmed

Example Find a ROM-based circuit implementation for: Solution: f(a,b,c) = a’b’ + abc g(a,b,c) = a’b’c’ + ab + bc h(a,b,c) = a’b’ + c Solution: Express f(), g(), and h() in m() format (use truth tables) Program the ROM based on the 3 m()’s

Example (cont.) There are 3 inputs and 3 outputs, thus we need a 8x3 ROM block. f = m(0, 1, 7) g = m(0, 3, 6, 7) h = m(0, 1, 3, 5, 7) a 1 2 3 4 5 6 7 3-to-8 decoder b c f g h

Programmable Logic Arrays (PLA) Similar concept as in ROM, except that a PLA does not necessarily generate all possible minterms (ie. the decoder is not used). More precisely, in PLAs both the AND and OR arrays can be programmed (in ROM, the AND array is fixed – the decoder – and only the OR array can be programmed).

Programmable Logic Arrays (PLA) A PLA consists of wide input programmable AND gates followed by a programmable OR gate plane. The routing architecture in a PLA is simple where every output is connected to every input through one switch. The switches are organized into crossbar-like structures. As such, PLAs are suitable for implementing logic in two-level sum-of-products form.

Programmable Logic Arrays (PLA)

PLA Example f(a,b,c) = a’b’ + abc g(a,b,c) = a’b’c’ + ab + bc h(a,b,c) = c PLAs can be more compact implementations than ROMs, since they can benefit from minimizing the number of products required to implement a function AND array OR array

Another PLA Example Find a PLA-based circuit implementation for: F1(A,B,C) = AB’ + AC + A’BC’ F2(A,B,C) = (AC + BC)’ Solution: 3 inputs, 2 outputs ( 2 OR gates) 4 distinct product terms (4 AND gates) Use XOR array to find complements

PLA Example (cont.) XOR array F2’ F1

PLA Example (cont.) Tabular Form Specification of interconnection programming F1 = AB’+AC+A’BC’ F2 = AC+BC

Determining the size of a PLA Given: n inputs p product terms m outputs PLA size is: Gates: n INV (and maybe n BUF) + p ANDs + m ORs + m XORs Programmable interconnections: 2np + pm + 2m

Programmable Array Logic (PAL) OR plane (array) is fixed, AND plane can be programmed Less flexible than PLA # of product terms available per function (OR outputs) is limited

Programmable Array Logic (PAL) PALs offers one level of programmability where inputs can be connected to programmable AND gates followed by a fixed OR gate plane. In order to support sequential circuits, the OR gates are usually followed by flip-flops. PALs are easier to program than PLAs, but they are not as flexible.

Programmable Array Logic (PAL)

PAL Example inputs 1st output section 2nd output Only functions with at most four products can be implemented 3rd output section 4th output section

PAL-based circuit implementation W = ABC + CD X = ABC + ACD + ACD + BCD Y = ACD + ACD + ABD

Can we implement more complex functions using PALs? Yes, by allowing output lines to also serve as input lines in the AND plane.

Example Implement the combinational circuit described by the following equations, using a PAL with 4 inputs, 4 outputs, and 3-wide AND-OR structure. W(A,B,C,D) = m(2,12,13) X(A,B,C,D) = m(7,8,9,10,11,12,13,14,15) Y(A,B,C,D) = m(0,2,3,4,5,6,7,8,10,11,15) Z(A,B,C,D) = m(1,2,8,12,13)

Example (cont.) Use function simplification techniques to derive: W = ABC’+A’B’CD’ X = A+BCD Y=A’B+CD+B’D’ Z=ABC’+A’B’CD’+AC’D’+A’B’C’D = W + AC’D’+A’B’C’D

Example (cont.)

Example (cont.) Tabular Form Specification of interconnection programming

Complex Programmable Logic Devices (CPLD) Multiple PLDs can be combined on a single chip by using programmable interconnect structures. These PLDs are called CPLDs.

FPGAs FPGAs are somewhat similar to CPLDs. However, the latter tend to have a more predictable delay due to their interconnect structure.

Implementation Strategies BCD to Excess 3 Converter D2 = Q2 • Q0 + Q2 • Q0 D1 = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0 D0 = Q0 Z = X• Q1 + X • Q1

Implementation Strategies BCD to Excess 3 Serial Converter 10H8 PAL: 10 inputs, 8 outputs, 2 product terms per OR gate D1 = D11 + D12 D11 = X • Q2 • Q1 • Q0 + X • Q2 • Q0 D12 = X • Q2 • Q0 + Q1 • Q0 0. Q2 • Q0 1. Q2 • Q0 8. X • Q2 • Q1 • Q0 9. X • Q2 • Q0 16. X • Q2 • Q0 17. Q1 • Q0 24. D11 25. D12 32. Q0 33. not used 40. X • Q1 41. X • Q1

Implementation Strategies BCD to Excess 3 Serial Converter

Implementation Strategies More Advanced PAL Architectures Buffered Input or product term Registered PAL Architecture Negative Logic Feedback D2 = Q2 • Q0 + Q2 • Q0 D1 = X • Q2 • Q1 • Q0 + X • Q2 + X • Q0 + Q2 • Q0 + Q1 • Q0 D0 = Q0 Z = X • Q1 + X • Q1

Programming Technology The first user programmable switch is the fuse used in simple PLDs. For high density devices (CPLDs, FPGAs), different approaches are used to achieve programmability. The properties of these programmable switches, such as size, volatility, process technology, on-resistance, and capacitance, determine the major features of an FPLD architecture.