3 Why Programmable Logic? Small and Medium Scale IntegrationUp to 200 gates per device/ICMost common is 74xx series (gates, FF, Decoders …)AdvantagesEasy to understand functionsExceptional Signal VisibilityDisadvantagesLow logic density means big boards or small designsHigher power consumptionFailure concern per function
4 Why Programmable Logic? Large Scale IntegrationRanging from 200 to 200,000 gates per device.Small memories, programmable logic devicesAdvantagesHigher logic density means smaller boards or larger designs.Many devices can be programmed and reprogrammed, saving expense when changes are made.DisadvantagesNeed to learn how to use and programSignal visibility is reduced
5 Why Programmable Logic ? Many programmable logic devices are field- programmable, i. e., can be programmed outside of the manufacturing environmentMost programmable logic devices are erasable and reprogrammable.Allows “updating” a device or correction of errorsAllows reuse the device for a different design - the ultimate in re-usability!Ideal for course laboratories
6 Programmable Configurations Read Only Memory (ROM) - a fixed array of AND gates and a programmable array of OR gatesProgrammable Array Logic (PAL) - a programmable array of AND gates feeding a fixed array of OR gates.Programmable Logic Array (PLA)Ò - a programmable array of AND gates feeding a programmable array of OR gates.PAL is a registered trademark of Lattice Semiconductor Corp.
7 Gate SymbolsFigure 6-18 Conventional and Array Logic Symbols for OR Gate
8 Read Only MemoryRead Only Memories (ROM) or Programmable Read Only Memories (PROM) are OP logic devices with a fixed AND array and a programmable OR array.have:k input lines,m output lines, andm = 2k decoded mintermsn OR gatesUsually referred as 2k x n ROMCan implement n functionswith k inputsk-to-2k line decoderD7D6D5D4D3D2D1D0A2A1A0ABCF0F1F2F3X
9 Read Only MemoryA program for a ROM or PROM is simply a multiple-output truth tableIf a 1 entry, a connection is made to the corresponding minterm for the corresponding outputIf a 0, no connection is madeThere is no advantage of simplifying the function when using ROM since we need to specify the entire list of minterms.Can be viewed as a memory with the inputs as addresses of data (output values), hence ROM or PROM names!
10 Read Only Memory Example Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)The fixed "AND" array is a “decoder” with 3 inputs and 8 outputs implementing minterms.The programmable "OR“ array uses a single line to represent all inputs to an OR gate. An “X” in the array corresponds to attaching the minterm to the ORRead Example: For input (A2,A1,A0) = 001, output is (F3,F2,F1,F0 ) = 0011.What are the simplified expressions for F3, F2 , F1 and F0 in terms of (A2, A1, A0)?D7D6D5D4D3D2D1D0A2A1A0ABCF0F1F2F3XF3 = D7 + D5 + D2 = A2 A0 + A2’ A1 A0’F2 = D7 + D0 = A2 A1 A0 + A2’ A1’ A0’F1 = D4 + D1 = A1 A1’ A0’ + A2’ A1’ A0F0 = D7 + D5 + D1 = A2 A0 + A1’ A0
11 Programmable Array Logic (PAL) PAL is the opposite of ROM; it is PLD that has a programmable AND array and a fixed OR array.Function has to be reduced into SOP before it is programmed into the PALDisadvantageROM guaranteed to implement any M functions of N inputs. PAL may have too few inputs to the OR gates.AdvantagesFor given internal complexity, a PAL can have larger k (inputs) and n (outputs)Some PALs have outputs that can be complemented, adding POS functions
13 Programmable Logic Array (PLA) Compared to a ROM and a PAL, a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs.A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL OR gatesSome PLAs have outputs that can be complemented (using XOR gates), adding POS functions
14 Programmable Array Logic (PLA) The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs.Fuse intactFuse blown1F2XABC34A BA CB C3-input, 3-output PLA with 4 product termsUsed to produce POS or complement of function