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CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina.

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Presentation on theme: "CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina."— Presentation transcript:

1 CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina

2 Chapter 5: Designing Combinational Systems

3 10/13/20093 Iterative System A system implemented with multiple copies of a smaller circuit Consider 4-bit adder as an example

4 10/13/20094 Delay in Combinational Logic Circuits When the input to a gate changes, the output of that gate will not change instantaneously Instead, there is a small delay ∆ If the output of one gate is used as the input to another gate, the delays will add The output is stable after the longest delay path

5 10/13/20095 Delay in Combinational Logic Circuits Hazard (or glitch)

6 10/13/20096 Example of Delay

7 10/13/20097 Cascading 4-bit Adders Can cascade multiple 4-bit adders if larger adders are needed

8 10/13/20098 Subtractors and Add/Subtractors To do subtraction, we can develop a 1-bit full subtractor and cascade as many of them as necessary On the other hand, we can build an add/subtractor based on an adder because a – b = a + (-b) Will need a signal line which is 0 for addition and 1 for subtraction (called a’/s, i.e. add’/subtract) This is because 1  x = x’ and 0  x = x

9 10/13/20099 Subtractors and Add/Subtractors

10 10/13/200910 Binary Decoder A binary decoder is a device that, when activated, selects one of several output lines, based on a coded input signal The input is an n-bit binary number, and there are 2 n output lines Some decoders also have one or more enable inputs Often used to select one of many devices

11 10/13/200911 Active High Decoder

12 10/13/200912 Active Low Decoder

13 10/13/200913 Decoder with Enable

14 10/13/200914 74138 Decoder

15 10/13/200915 74138 Decoder

16 10/13/200916 Use Decoder to Enable Another Decoder

17 10/13/200917 Multiplexers A multiplexer is a switch that passes one of its data inputs through to the output, as a function of a set of select inputs Sets of multiplexers are often used to choose among several multibit input numbers

18 10/13/200918 Two-way Multiplexer out = w if S = 0; out = x if S = 1

19 10/13/200919 Four-way Multiplexer

20 10/13/200920

21 10/13/200921 Three-variable Function Implemented with Multiplexer

22 10/13/200922 Demultiplexer Inverse of a mux: routes a signal from one place to one of many places

23 10/13/200923 Three-State Gates Has an enable input If the enable input is active, the gate behaves as usual If the enable input is inactive, the output behaves as if it is not connected

24 10/13/200924 A Multiplexer using Three- State Gates if EN = 0, f = a if EN = 1, f = b

25 10/13/200925 Gate Arrays Also known as programmable logic device (PLD) or field programmable gate array (FPGA) An efficient way of implementing complicated systems Can implement SOP expressions which are sums of some common product terms

26 10/13/200926 Structure of a Gate Array

27 10/13/200927 An Example of Gate Array f = a’b’ + abc g = a’b’c’ + ab + bc h = a’b’ + c

28 10/13/200928 Three Types of Combinational Logic Arrays Programmable Logic Array (PLA) User specifies all of the connections in both the AND array and the OR array Read-Only Memory (ROM) The AND array is fixed – like a decoder consisting of 2 n AND gates for n inputs User specifies the connections in the OR array Programmable Array Logic (PAL) The connections to the OR gates are specified; user determines the AND gate inputs

29 10/13/200929 Only need a list of minterms for each function. For example, W(A, B, C, D) = ∑m(3, 7, 8, 9, 11, 15) X(A, B, C, D) = ∑m(3, 4, 5, 7, 10, 14, 15) Y(A, B, C, D) = ∑m(1, 5, 7, 11, 15) Design with Read-Only Memories

30 10/13/200930 Structure of a PAL

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