Chapter # 4: Programmable and Steering Logic Section 4.1
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1 Chapter # 4: Programmable and Steering Logic Section 4.1
2 PALs and PLAsPre-fabricated building block of many AND/OR gates (or NOR, NAND)"Personalized" by making or breaking connections among the gatesProgrammable Array Block Diagram for Sum of Products Form
3 PLA -- Programmable Logic Array PAL -- Programmable Array Logic PALs and PLAsPLA -- Programmable Logic ArrayPAL -- Programmable Array LogicA typical TTL field-PLA might have 16 inputs, 48 product terms, 8 outputs data pinsEquivalent -- forty-eight 16-input AND gates and eight 48-input OR gates.12 data-pin SSI package gives four 2-input gate
4 PALs and PLAsKey to Success: Shared Product TermsEquationsF0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + AExample:Input Side:1 = asserted in term0 = negated in term- = does not participatePersonality MatrixOutput Side:1 = term connected to output0 = no connection to outputNeed a 3-input, 5-product term, 4-output --- PLA device
5 All possible connections are available PALs and PLAsExample ContinuedAll possible connections are availablebefore programmingABCF0F1F2F3
6 Programmer -- hardware device which personalizes the array PALs and PLAsExample ContinuedProgrammer -- hardware device which personalizes the arrayProgramming process depends on the particular ICFrequent technique -- places fuses between all possible inputs to a gate and the gate itself. Programmer hardware breaks the connections by placing a high current across selected fuses
7 Unwanted connections are "blown" PALs and PLAsExample ContinuedABCUnwanted connections are "blown"ABB’CAC’F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + AB’C’ANote: some array structureswork by making connectionsrather than breaking themF0F1F2F3
8 Function Generator of 3 inputs: A, B, C PALs and PLAsDesign ExampleABCFunction Generator of 3 inputs: A, B, CThe circuit should implement the logicfunctions AND, OR, NAND, NOR, XOR,XNORABCABCA’B’F1 = A B CF2 = A + B + CF3 = A B C = A’ + B’ + C’F4 = A + B + C = A’B’C’F5 = A B C = A’B’C + A’BC’ + AB’C’+ ABCF6 = A B C = ABC’ + A’BC + AB’C+ A’B’C’C’A’B’C’A’B’CA’BC’AB’C’ABC’A’BCAB’CF1F2F3F4F5F6
9 Notation for implementing PALs and PLAsAlternative representation for high fan-in structures4-input, 4-output, 4 product termsShort-hand notationso we don't have todraw all the wires!ABCDNotation for implementingF0 = A B + A' B'F1 = C D' + C' DAB + A’B’CD’ + C’D
10 What is difference between Programmable Array Logic (PAL) and PALs and PLAsWhat is difference between Programmable Array Logic (PAL) andProgrammable Logic Array (PLA)?PAL concept — implemented by Monolithic Memories. Programmable AND array but connections between product terms and specific OR gates are hardwire (constrained topology of the OR Array).A given column of the OR arrayhas access to only a subset ofthe possible product termsPLA concept — generalized topologies in AND and OR planes. Can be programmed in any way.PLA can take advantage of shared product terms. PAL cannot. PLA is slowerbecause of the relative resistance of programmable and hardwired connections.
11 PALs and PLAsDesign Example: BCD to Gray Code ConverterTruth TableK-mapsMinimized Functions:W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'
12 No shared product terms, PAL implementation is best. Programmed PAL: PALs and PLAsABCDNo shared product terms,PAL implementation is best.Programmed PAL:4 inputs,16 Programmable ANDS4 4-input ORS4 outputsABDBCBC’BCA B C DBCDAD’B’CD’4 product terms per each OR gateWXYZ
13 PALs and PLAsCode Converter Discrete Gate Implementation5 SSI Packages vs. 1 PLA/PAL Package!
14 PALs and PLAsAnother Example: Magnitude ComparatorWhat is more efficient, a PLAor PAL?
15 Another Example: Magnitude Comparator (cont’d) PALs and PLAsAnother Example: Magnitude Comparator (cont’d)Since AC’ and A’C are used twice, (shared), a PLA-based implementation is better than a PAL..ABCDABCDABCDABCDABCDACACBDBDABDBCDABCBCDEQNELTGT