Introduction to Experiment 6 Internal FPGA Memories, Pseudo Random Number Generator, Advanced Testbenches ECE 448 Spring 2009.

Slides:

Advertisements

Similar presentations

Lecture 15 Finite State Machine Implementation

Advertisements

Lecture 11 Xilinx FPGA Memories

George Mason University ECE 448 – FPGA and ASIC Design with VHDL ECE 448 Lecture 10 Advanced Testbenches.

11/17/05ELEC / Lecture 201 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Fall 2006, Nov. 30 ELEC / Lecture 12 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Test Power Vishwani D.

Configurable System-on-Chip: Xilinx EDK

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts,

ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,

ECE 448 – FPGA and ASIC Design with VHDL Lecture 13 PicoBlaze I/O & Interrupt Interface.

ECE 448 – FPGA and ASIC Design with VHDL Lecture 15 External SRAM.

Spring 07, Jan 30 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 SOC Test Scheduling Vishwani D. Agrawal James.

Basic Adders and Counters Implementation of Adders in FPGAs ECE 645: Lecture 3.

Constructive Computer Architecture Tutorial 4: SMIPS on FPGA Andy Wright 6.S195 TA October 7, 2013http://csg.csail.mit.edu/6.s195T04-1.

ECE 2372 Modern Digital System Design

George Mason University FPGA Memories ECE 448 Lecture 13.

Lecture 9 RTL Design Methodology Sorting Example.

ECE 448 – FPGA and ASIC Design with VHDL Lecture 11 Memories in Xilinx FPGAs.

ECE 449: Computer Design Lab Coordinator: Kris Gaj TAs: Tuesday session: Pawel Chodowiec Thursday session: Nghi Nguyen.

ECE 448 – FPGA and ASIC Design with VHDL Lecture 12 PicoBlaze Overview.

ECE 448: Spring 11 Lab 3 Part 1 Sequential Logic for Synthesis.

ECE 448 – FPGA and ASIC Design with VHDL Lecture 12 PicoBlaze Overview.

Introduction to structured VLSI Projects 4 and 5 Rakesh Gangarajaiah

Lecture #27 Page 1 ECE 4110– Sequential Logic Design Lecture #27 Agenda 1.Counters Announcements 1.HW #12 due.

Introduction to Experiment 7 Sorting Using PicoBlaze ECE 448 Spring 2010.

ECE 448: Lab 6 DSP and FPGA Embedded Resources (Digital Downconverter)

George Mason University ECE 449 – Computer Design Lab Welcome to the ECE 449 Computer Design Lab Spring 2005.

George Mason University ECE 449 – Computer Design Lab Welcome to the ECE 449 Computer Design Lab Spring 2004.

Reaction Timer Project

Introduction to FPGA Tools

RTL Design Methodology Transition from Pseudocode & Interface

CDA 4253 FGPA System Design Xilinx FPGA Memories

Lecture 5B Block Diagrams HASH Example.

Lecture 10 Xilinx FPGA Memories Part 1

ECE 448: Lab 6 Using PicoBlaze Fast Sorting. Part 1: Introduction to Lab 6 Part 2: Instruction Set of PicoBlaze-6 Part 3: Hands-on Session: OpenPICIDE.

Lecture 13 PicoBlaze I/O & Interrupt Interface Example of Assembly Language Routine ECE 448 – FPGA and ASIC Design with VHDL.

CDA 4253 FPGA System Design RTL Design Methodology 1 Hao Zheng Comp Sci & Eng USF.

Teaching Digital Logic courses with Altera Technology

Introduction to Experiment 7 Replacing Hardwired Control Unit with the Picoblaze Microcontroller ECE 448 Spring 2009.

ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.

CDA 4253 FPGA System Design Final Project Hao Zheng Comp Sci & Eng U of South Florida 1.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL FPGA Devices ECE 448 Lecture 5.

Lecture 11 Xilinx FPGA Memories Part 2

George Mason University Advanced Testbenches Lecture 4.

ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and ISim. Using Seven-Segment Displays, Buttons, and Switches.

RTL Hardware Design by P. Chu Chapter 9 – ECE420 (CSUN) Mirzaei 1 Sequential Circuit Design: Practice Shahnam Mirzaei, PhD Spring 2016 California State.

ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and Isim. Using Seven-Segment Displays, Buttons, and Switches.

1 Modeling Synchronous Logic Circuits Debdeep Mukhopadhyay Associate Professor Dept of Computer Science and Engineering NYU Shanghai and IIT Kharagpur.

ECE 448 – FPGA and ASIC Design with VHDL George Mason University ECE 448 Lab 2 Implementing Combinational Logic in VHDL.

Introduction to the FPGA and Labs

Temperature Measurement

RTL Design Methodology

Implementing Combinational and Sequential Logic in VHDL

Lecture 18 PicoBlaze I/O Interface

RTL Design Methodology

ECE 448: Lab 6 Using PicoBlaze Fast Sorting Class Exercise 2.

Developing More Advanced Testbenches

Lecture 13 PicoBlaze I/O & Interrupt Interface

Using Fpro SoC with Hardware Accelerators

Sequential Logic for Synthesis Simulation using ModelSim

Implementing Combinational and Sequential Logic in VHDL

Lecture 13 PicoBlaze I/O & Interrupt Interface

Lecture 17 PicoBlaze I/O & Interrupt Interface

RTL Design Methodology

THE ECE 554 XILINX DESIGN PROCESS

RTL Design Methodology

RTL Design Methodology

RTL Design Methodology Transition from Pseudocode & Interface

ECE 448 Lab 3 – Part 1 FPGA Design Flow Based on

THE ECE 554 XILINX DESIGN PROCESS

Computer Architecture Assembly Language

Presentation transcript:

Introduction to Experiment 6 Internal FPGA Memories, Pseudo Random Number Generator, Advanced Testbenches ECE 448 Spring 2009

2ECE 448 – FPGA and ASIC Design with VHDL Sources Lecture 14 Xilinx FPGA Memories Lecture 11 Advanced Testbenches P. Chu, FPGA Prototyping by VHDL Examples Chapter 11, Xilinx Spartan-3 Specific Memory Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 14, starting from “Design Verification” (handout distributed in class)

3ECE 448 – FPGA and ASIC Design with VHDL Sources XAPP463 Using Block RAM in Spartan-3 Generation FPGAs Google search: XAPP463 XAPP464 Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs Google search: XAPP464 XST User Guide, Section: Coding Techniques Google search: XST User Guide (PDF) (HTML) ISE In-Depth Tutorial, Section: Creating a CORE Generator Module Google search: ISE In-Depth Tutorial

Addr Din Dout PRNG SORTING/ EDIT RAM CONTROL INPUT INTERFACE OUTPUT INTERFACE CURRENT ADDRES joystick Two 7-segment displays 8 LEDs Curr_Addr from CONTROL

Task 1 – Browsing Mode …. FA FB FC FD FE FF …. FA FB FC FD FE FF AddressData Current Address Two 7-Segment Displays (in hexadecimal notation) Joystick up = Increment Address Joystick down = Decrement Address 8 LEDs (in binary notation) Value at Current Address 256x8 RAM

Task 2 – Edit Mode …. FA FB FC FD FE FF =>06 …. FA FB FC FD FE FF AddressData Current Address Two 7-Segment Displays (in hexadecimal notation) Joystick up = Increment Address Joystick down = Decrement Address 8 LEDs (in binary notation) Value at Current Address 256x8 RAM Joystick Enter = Edit Joystick up = Increment Data Joystick down = Decrement Data Joystick Enter = Approve

Task 3 – Initialize …. FA FB FC FD FE FF B5 C6 …. 7A 5B AddressData Joystick Enter = Initialize with Pseudorandom Values 256x8 RAM

Pseudo Random Number Generator (PRNG) A pseudorandom number generator (PRNG) is an algorithm for generating a sequence of numbers that approximates the properties of random numbers. The sequence is not truly random in that it is completely determined by a relatively small set of initial values. A PRNG can be started from an arbitrary starting state, using a seed state. It will always produce the same sequence thereafter when initialized with that state. The maximum length of the sequence before it begins to repeat is determined by the size of the state, measured in bits. PRNG Circuit can be constructed from a Linear Feedback Shift Register (LFSR) circuit *from

Linear Feedback Shift Register (LFSR) A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. The only linear functions of single bits are xor and inverse-xor; thus it is a shift register whose input bit is driven by the exclusive-or (xor) of some bits of the overall shift register value. *from

8-bit LFSR (Linear Feedback Shift Register) with the period of R R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7 = D flip-flop with set or reset determining its initial value after “soft” reset Run for 8 clock cycles before using a new output value.

Task 4 – Sorting …. FA FB FC FD FE FF …. B4 B6 B8 CC D4 FF AddressData Joystick Enter = sorting using one of the following types sorting signed numbers in the descending order sorting signed numbers in the ascending order sorting unsigned numbers in the descending order sorting unsigned numbers in the ascending order Joystick Up changing sorting type 256x8 RAM

Task 5 – Advanced Testbench Processes Generating Input Stimuli Design Under Test (DUT) Process Comparing Actual Outputs vs. Expected Outputs Design Correct/Incorrect Yes/No Testvector file(s)

Task 5 – Format of an input file number of entries to be sorted (in decimal) empty line numbers to be sorted in the initial order (in the hexadecimal notation, one number per line) empty line numbers after sorting (in the hexadecimal notation, one number per line) 6 B4 89 A A3 B4

Task 6 : Different Memory Types Memory Distributed (MLUT-based) Block RAM-based (BRAM-based) Inferred Memory Manually Using Core Generator

Task 7: Dual-port Memory Replace Single-Port RAM with Dual-Port RAM and redesign Sorting Logic accordingly Calculate the gain in terms of - average execution time - smaller resource utilization.

Introduction to Core Generator (Hands-on Session)