1. Using Fpro SoC with Hardware Accelerators
ECE 448: Lab 5
Using Fpro SoC with Hardware Accelerators
Fast Sorting

2. Agenda for today Part 1: Introduction to Lab 5
Part 2: Lab 5 Exercise 1
Part 3: Lab 4 Demo

3. Part 1 Introduction to Lab 5
ECE 448 – FPGA and ASIC Design with VHDL

4. Required Reading P. Chu, FPGA Prototyping by VHDL Examples
Chapter 8: Overview of Embedded SoC Systems
Chapter 9: Bare Metal System Software Development
Chapter 10: FPro Bus Protocol and MMIO Slot Specification
Chapter 14: Debouncing Core and LED-Mux Core
Appendix A.4: Tutorial on IP Instantiation
Appendix A.5: Short Tutorial on FPro System Development
ECE 448 – FPGA and ASIC Design with VHDL

5. Recommended Materials
Book Website
Source Codes
read_me file: readme_source_code.pdf
source file: fpga_mcs_vhdl_src.zip (last updated 11/10/2017)
Basys 3 supplement materials
read_me file: readme_basys3_adoption.pdf
source file: basys3_supplement_src.zip (last updated 12/05/2017)
Project files w/ Basys 3 board (in Vivado v2017.2)
basys3_vanilla.xpr.zip
basys3_sampler.xpr.zip
basys3_daisy.xpr.zip
ECE 448 – FPGA and ASIC Design with VHDL

6. General Description Sorting in software (C/C++) using MicroBlaze
Sorting using a hardware accelerator written in RTL VHDL
Comparison of the execution times for
different number of elements to sort
from 28 to 220 (powers of two only)

7. Sorting
GPO2
GPI2
LED
Switches
SSEG
Buttons

8. Task 1 – Browsing Mode (default mode)
Two 7-Segment
Displays
(in hexadecimal
notation) (SSD3-SSD2)
Address
Data 00 01 02 03 04
05 …. FB FC FD FE FF 00 01 02 03 04
05 …. FB FC FD FE FF
Current Address
Value at
Current Address
Button Up =
Increment Address
Button Down =
Decrement Address
Two 7-Segment
Displays
(in hexadecimal
notation) (SSD1-SSD0)
256x8 RAM

9. Task 2 – Initialize in Software
Address
Data 00 01 02 03 04
05 …. FB FC FD FE FF 25 87 94 26 B5
C6 …. 7A 5B 34 43 89
Button Left =
Initialize with
Pseudorandom
Values
Then, return
to the browsing mode
256x8 RAM

10. Task 3 – Sorting Sorting signed numbers in the descending order
Address
Data
Sorting signed numbers in the descending order 00 01 02 03 04
05 …. FB FC FD FE FF 7F 67 53 44 38
2D …. B1 AA 91 80
256x8 RAM

11. Task 4 – Cycle Count Display Mode
During Sorting display: “----” on the Seven Segment Displays.
After Sorting display: Number of clock cycles used
(in the hexadecimal notation)
#Cycles15… least significant bits
#Cycles most significant bits
Switch between these two values using switch S7
S6=0 : 16 least significant bits
S6=1 : 16 most significant bits
Software vs. Hardware Sorting
S7=0 : Number of clock cycles in software
S7=1 : Number of clock cycles in hardware
Pressing any button (other than Select) after sorting, brings the display back to the browsing mode.

12. Task 5 – Size of Memory to Initialize & Sort
S5..S0 log2 of the number of elements to initialize and sort
Suggested values:
For debugging: meaning 16 elements
For demo: meaning 256 elements
For timing measurements to be included in the report:
meaning from 256 to 1M elements

13. Deliverables New VHDL Code New C/C++ Code New Constraint Files
VHDL Code of the Entire System (including code
accompanying the textbook)
5. Entire C/C++ Code Used (including code
6. Constraints files for the entire system
7. Report file

14. Report File List of fully completed tasks
List of partially completed tasks, including the
description of any missing functionality
3. Table showing for each number of memory
elements between 28 and 220 (powers of 2 only)
Execution time in software (clock cycles & ms)
Execution time in hardware (clock cycles & ms)
Ratio of the execution time in software vs. hardware

15. Contest for the Fastest Implementation of Sorting
Bonus points will be awarded to students who perform sorting (correctly) using the smallest number of clock cycles in hardware and/or software
Possible optimizations:
Faster sorting algorithms in software
Efficient C implementation
Faster sorting algorithms in hardware
Efficient VHDL implementation

16. Part 2
Lab 5 Exercise 1
ECE 448 – FPGA and ASIC Design with VHDL

17. Part 3
Lab 4 Demos
ECE 448 – FPGA and ASIC Design with VHDL