1. ECE 448 – FPGA and ASIC Design with VHDL Lecture 13 PicoBlaze I/O & Interrupt Interface

2. 2 ECE 448 – FPGA and ASIC Design with VHDL Required reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 16, PicoBlaze I/O Interface Chapter 17, PicoBlaze Interrupt Interface

3. 3 Output Decoding of Four Output Registers ECE 448 – FPGA and ASIC Design with VHDL

4. 4 Timing Diagram of an Output Instruction ECE 448 – FPGA and ASIC Design with VHDL

5. 5 Truth Table of a Decoding Circuit ECE 448 – FPGA and ASIC Design with VHDL

6. 6 Block Diagram of Four Continuous-Access Ports ECE 448 – FPGA and ASIC Design with VHDL

7. 7 Timing Diagram of an Input Instruction ECE 448 – FPGA and ASIC Design with VHDL

8. 8 Block Diagram of Four Single-Access Ports ECE 448 – FPGA and ASIC Design with VHDL

9. 9 FIFO Interface ECE 448 – FPGA and ASIC Design with VHDL FIFO clk rst 8 din dout full empty writeread clkrst 8

10. 10 Operation of the First-Word Fall-Through FIFO ECE 448 – FPGA and ASIC Design with VHDL

11. 11 Operation of the “Standard” FIFO ECE 448 – FPGA and ASIC Design with VHDL −−−−− ABCD

12. 12 Interrupt Flow ECE 448 – FPGA and ASIC Design with VHDL

13. 13 Timing Diagram of an Interrupt Event ECE 448 – FPGA and ASIC Design with VHDL

14. 14 ECE 448 – FPGA and ASIC Design with VHDL

15. 15 Interrupt Interface with a Single Event ECE 448 – FPGA and ASIC Design with VHDL

16. 16 Interrupt Interface with Two Requests ECE 448 – FPGA and ASIC Design with VHDL

17. 17 Time-Multiplexed Seven Segment Display ECE 448 – FPGA and ASIC Design with VHDL

18. 18 Block Diagram of the Hexadecimal Time-Multiplexing Circuit ECE 448 – FPGA and ASIC Design with VHDL

19. 19 Hexadecimal Multiplexing Circuit Based on PicoBlaze and mod-500 Counter ECE 448 – FPGA and ASIC Design with VHDL