1. Introduction to Experiment 7 Sorting Using PicoBlaze ECE 448 Spring 2010

2. 2ECE 448 – FPGA and ASIC Design with VHDL Sources P. Chu, FPGA Prototyping by VHDL Examples Chapter 14, Picoblaze Overview Chapter 15, Picoblaze Assembly Code Development Chapter 16, Picoblaze I/O Interface Chapter 17, Picoblaze Interrupt Interface

4. 000 001 002... 0FE 0FF 100 101 102 103 104 105 106 107 108 1FE 1FF 255 x 8 DATA RAM MEM_BANK BUTTON SSD3 SSD2 LED PRNG_STATUS PRNG_CTRL MEM_BANK MEM_BANK: 7 6 5 4 3 2 1 0 A8 A8 – current memory bank number = the most significant bit of the address BUTTON: 7 6 5 4 3 2 1 0 A A – button active (bit cleared by reading register BUTTON or by interrupt_ack), b3-b0 – buttons 3 to 0 respectively For all modes, button 2 switches to the next mode. b0b1b2b3 PRNG_STATUS: 7 6 5 4 3 2 1 0 D D – done: bit cleared by writing to register PRNG_CTRL, set after PRNG generates 255 8-bit numbers, PRNG_CTRL: 7 6 5 4 3 2 1 0 I I – initialize: after 1 is written to this bit, PRNG generates 255 8-bit numbers, and the corresponding address (index) of each number SSD1 SSD0 SWITCH

5. SWITCH: 7 6 5 4 3 2 1 0 S0 S7-S0 – bits correspond to the state of each switch S1S2S3S4S5S6S7

6. Task 1 – Browsing Mode 00 01 02 03 04 05 …. FA FB FC FD FE 00 01 02 03 04 05 …. FA FB FC FD FE AddressData Current Address Two 7-Segment Displays (in hexadecimal notation) (SSD1-SSD0) Button 1 = Increment Address Button 0 = Decrement Address Value at Current Address 255x8 RAM Two 7-Segment Displays (in hexadecimal notation) (SSD3-SSD2)

7. Task 2 – Edit Mode 00 01 02 03 04 05 …. FA FB FC FD FE 00 01 02 03 04 05=>06 …. FA FB FC FD FE AddressData Current Address Two 7-Segment Displays (SSD1-SSD0) (in hexadecimal notation) Button 1 = Increment Address Button 0 = Decrement Address Value at Current Address 255x8 RAM Button 3= Edit Button 1 = Increment Data Button 0 = Decrement Data Button 3= Approve Two 7-Segment Displays (SSD3-SSD2) (in hexadecimal notation)

8. Task 3 – Initialize 00 01 02 03 04 05 …. FA FB FC FD FE 25 87 94 26 B5 C6 …. 7A 5B 34 43 89 AddressData Button 3 = Initialize with Pseudorandom Values 255x8 RAM

9. 8-bit LFSR (Linear Feedback Shift Register) with the period of 2 8 -1 8 R R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7 = D flip-flop with set or reset determining its initial value after “soft” reset Run for 8 clock cycles before using a new output value.

10. Task 4 – Sorting 00 01 02 03 04 05 …. FA FB FC FD FE 25 37 44 56 57 78 …. B4 B6 B8 CC D4 AddressData Button 3= sorting using one of the following modes sorting signed numbers in the descending order sorting signed numbers in the ascending order sorting unsigned numbers in the descending order sorting unsigned numbers in the ascending order Switches 7-6 control the sorting type “00”- signed descending “01”- signed ascending “10” - unsigned descending “11” – unsigned ascending 255x8 RAM

11. Task 5 – Advanced Testbench Processes Generating Input Stimuli Design Under Test (DUT) Process Comparing Actual Outputs vs. Expected Outputs Design Correct/Incorrect Yes/No Testvector file(s)

12. Task 5 – Format of an input file number of entries to be sorted (in decimal) empty line numbers to be sorted in the initial order (in the hexadecimal notation, one number per line) empty line numbers after sorting (in the hexadecimal notation, one number per line) 6 B4 89 A3 58 61 78 58 61 78 89 A3 B4

13. Extra Credit Implement keyboard input using the arrow keys using the PS/2 connector in order to replace the buttons. Implement mouse input by using the mouse to click on quadrants on the screen representing different buttons.

14. Extra Credit

15. Introduction to Picoblaze Development Environment (Hands-on Session)