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Sequential Logic for Synthesis Simulation using ModelSim
ECE 448: Spring 13 Lab 3 Sequential Logic for Synthesis Simulation using ModelSim Add design flow from lecture 1 Why are we interested in PRNG Generate with R=8 Reduce PRNG to 3 slides: purpose, GIF, example Add Loading circuit for PRNG
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Agenda for today Part 1: Introduction to Lab 3 Top-level circuit LFSR
MISR Debouncer Edge Detector Part 2: Hands-on Session: Simulation Using ModelSim Part 3: Demos of Lab 2
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Part 1 Introduction to Lab 3
ECE 448 – FPGA and ASIC Design with VHDL
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Top-Level Circuit 4
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LAB2 A B X Y sel En ‘0’ LFSR CNTR UP = X”3FF” ≠ 0 MISR rst clk en ld
8 IVB loadB OR nexti 1 cnz IVA loadA LAB2 A B X Y sel En ‘0’ YSGN next XSGN 10 k k9..8 2 k7..0 ≠ 0 = X”3FF” done AND not done step run
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Source of Inputs & Display of Outputs
(to be experimentally tested in Lab 4) Used to display XSGN, YSGN Used to enter IVA, IVB Used to generate loadA, loadB, step, run
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Connection of Buttons to the Pins of FPGA
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Generation of Inputs Using Buttons
RESET BTNL BTNR BTNU BTNS Debouncer RED loadA loadB step rst run D Q ‘1’ en clk RED = Rising Edge Detector
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Pseudo-Random Number Generators Implemented Using LFSRs
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PRNG Generates a sequence of numbers that approximates the properties of random numbers. The sequence is fully deterministic, i.e., it can be repeated based on an initial state of PRNG. The period of the sequence may be made very large (typically, 2n-1, where n is an internal state size)
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PRNG Random Numbers are often important Testing of VLSI circuits
Cryptography Monte Carlo simulations Noise addition Bit error detection, and many other applications
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Linear Feedback Shift Register (LFSR)
Each stage = D flip-flop L, C(D) Length Connection polynomial, C(D) C(D) = 1 + c1D + c2D cLDL
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sj = c1sj-1 c2sj-2 . . . cL-1sj-(L-1) cLsj-L
Initial state [sL-1, sL-2, , s1, s0] LSFR recursion: sj = c1sj-1 c2sj-2 cL-1sj-(L-1) cLsj-L for j L
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Example of LFSR 4, 1+D+D4 Length Connection polynomial, C(D)
C(D) = 1 + 1D + 0D2 + 0D3 + 1D4 c1=1 c2=0 c3=0 c4=1
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LFSR State Sequence s4 s3 s2 s1 s0
s4 = c1s3 c2s2 c3s1 c4s0 = s3 s0
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LFSR to be used in Lab 3 Selected to make a period = 28-1 = 255
8, 1+D4+D5+D6+D8 Length Connection polynomial, C(D) Selected to make a period = 28-1 = 255
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Initializing Serial Shift Register with Parallel Load
Sin D Q D Q D Q D Q Clock Enable Q(3) Q(2) Q(1) Q(0) Hint: Use similar technique for initializing LFSR
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Multiple Input Signature Register
MISR 18
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MISR is used to compress multiple inputs D
MISR - Multiple Input Signature Register D7 D6 D5 D4 D3 D2 D1 D0 rst rst rst rst rst rst rst rst rst rst rst rst rst rst rst rst D Q D Q D Q D Q D Q D Q D Q D Q en en en en en en en en en Q7 en Q6 en Q5 en Q4 en Q3 en Q2 en Q1 en Q0 AND C7 AND C6 AND C5 AND C4 AND C3 AND C2 AND C1 AND C0 MISR is used to compress multiple inputs D to a single signature Q C=C7..C0 should be declared as a generic in VHDL code For the purpose of testing set C=X”B8”
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Debouncer 20
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Debouncer Capacitance in the button and contacts “bouncing” causes spurs that cause false positives. A debouncing circuit removes these spurs. This graphs shows releasing a button.
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Debouncer When the first change is detected, we ignore all subsequent changes for some period of time, preferably until all of the bouncing would have occurred. This is usually in the order of ms.
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Debouncer Debouncer reset output input clk
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Debouncer
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Rising Edge Detector RED
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Rising Edge Detector - RED
Turn a step function into an impulse Allows a step to run a circuit for only one clock cycle
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Rising Edge Detector reset input output clk clk input output
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Simulation Using ModelSim
Part 2 Hands-on Session Simulation Using ModelSim ECE 448 – FPGA and ASIC Design with VHDL
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Hands-on Session on ModelSim using four_bit_counter based on JK flip-flops
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Part 3 Lab 2 Demos ECE 448 – FPGA and ASIC Design with VHDL
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