ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2014 Power and Ground Vishwani D. Agrawal James J. Danaher Professor ECE.

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Presentation transcript:

ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2014 Power and Ground Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL Spring 2014, Mar 21...

References  Q. K. Zhu, Power Distribution Network Design for VLSI, Hoboken, New Jersey: Wiley,  M. Popovich, A. Mezhiba and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Springer,  C.-K. Koh, J. Jain and S. F. Cauley, “Synthesis of Clock and Power/Ground Network,” Chapter 13, L.-T. Wang, Y.-W. Chang and K.-T. Cheng (Editors), Electronic Design Automation, Morgan- Kaufmann, pp  J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, Z. Pan, “VLSI On-Chip Power/Ground Network Optimization Considering Decap Leakage Currents,” Proc. Asia and South Pacific Design Automation Conf., 2005, pp  Decoupling Capacitors, Articles/decoupling-capacitors.html Articles/decoupling-capacitors.html Articles/decoupling-capacitors.html ELEC 7770: Advanced VLSI Design (Agrawal)2Spring 2014, Mar 21...

Supply Voltage ELEC 7770: Advanced VLSI Design (Agrawal) Minimum feature size (μm) Supply voltage (V) Spring 2014, Mar 21...

Gate Oxide Thickness ELEC 7770: Advanced VLSI Design (Agrawal) Minimum feature size (μm) Gate oxide thickness (A) High gate leakage Spring 2014, Mar 21...

Power Supply Noise  Transient behavior of supply voltage and ground level.  Caused by transient currents:  Power droop  Ground bounce ELEC 7770: Advanced VLSI Design (Agrawal)5Spring 2014, Mar 21...

Power Supply ELEC 7770: Advanced VLSI Design (Agrawal)6 +–+– Gate 1 Gate 2 VDD Rg RCRC RCRC V(t) Spring 2014, Mar 21...

Switching Transients  Only Gate 1 switches (turns on): V(t) = VDD – Rg VDD exp[– t/{C(R+Rg)}]/(R+Rg) ELEC 7770: Advanced VLSI Design (Agrawal)7 V(t) VDD 0time, t VDD Rg/(R+Rg) Spring 2014, Mar 21...

Multiple Gates Switching ELEC 7770: Advanced VLSI Design (Agrawal)8 Gate output voltage VDD 0time, t many Number of gates switching Spring 2014, Mar 21...

Decoupling Capacitor  A capacitor to isolate two electrical circuits.  Illustration: An approximate model: ELEC 7770: Advanced VLSI Design (Agrawal)9 +–+– VDD = 1 Rg Rd Cd IL VL(t) t i(t) a t=0 Spring 2014, Mar 21...

Approximate Load Current, IL 0,t < 0 at,t < tp IL= a(2tp – t),t < 2tp 0,t > 2tp ELEC 7770: Advanced VLSI Design (Agrawal)10Spring 2014, Mar 21...

Transient Load Voltage VL(t) = 1 – a Rg [ t – Cd Rg (1 – e – t/T ) ], 0 < t < tp T=Cd (Rg + Rd) ELEC 7770: Advanced VLSI Design (Agrawal)11Spring 2014, Mar 21...

Realizing Decoupling Capacitor ELEC 7770: Advanced VLSI Design (Agrawal)12 GND SB D VDD GND SB D VDD OR Spring 2014, Mar 21...

Capacitance Cd=γ×WL×ε×ε 0 /Tox ≈0.26fF, for 70nm BSIM L=38nm,W=200nm γ= ε=4 ELEC 7770: Advanced VLSI Design (Agrawal)13Spring 2014, Mar 21...

Leakage Resistance Igate=α × e – βTox ×W where α and β are technology parameters. Rd=VL(t)/Igate Because V(t) is a function of time, Rd is difficult to estimate. The decoupling capacitance is simulated in spice. ELEC 7770: Advanced VLSI Design (Agrawal)14Spring 2014, Mar 21...

Power-Ground Layout ELEC 7770: Advanced VLSI Design (Agrawal)15 Vss Vdd Vss Vdd Solder bump pads M5 M4 Via Vdd/Vss supply Vdd/Vss equalization Spring 2014, Mar 21...

Power Grid ELEC 7770: Advanced VLSI Design (Agrawal)16 +–+– Spring 2014, Mar 21...

Nodal Analysis ELEC 7770: Advanced VLSI Design (Agrawal)17 V1 V2 V3 V4 Ci Vi Bi Apply KCL to node i: 4 ∑ (Vk – Vi) gk – Ci ∂Vi/∂t = Bi k=1 g1 g2 g3 g4 Spring 2014, Mar 21...

Nodal Analysis ELEC 7770: Advanced VLSI Design (Agrawal)18 G V – C V’ = B WhereG is conductance matrix V is nodal voltage vector C is admittance matrix B is vector of currents V(t) is a function of time, V(0) = VDD B(t) is a function of time, B(0) ≈ 0 or leakage current Spring 2014, Mar 21...

Wire Width Considerations  Increase wire width to reduce resistance:  Control voltage drop for given current  Reduce resistive loss  Reduce wire width to reduce wiring area.  Minimum width restricted to avoid metal migration (reliability consideration). ELEC 7770: Advanced VLSI Design (Agrawal)19Spring 2014, Mar 21...

A Minimization Problem ELEC 7770: Advanced VLSI Design (Agrawal)20 Minimize total metal area: n A= ∑ w i s i =∑ | ρ C i s i 2 | / x ii=1 Where n=number of branches in power network w i =metal width of ith branch s i =length of ith branch ρ=metal resistivity C i =maximum current in ith branch x i =voltage drop in ith branch Subject to several conditions. Spring 2014, Mar 21...

Condition 1: Voltage Drop ELEC 7770: Advanced VLSI Design (Agrawal)21 Voltage drop on path P k : ∑ x i ≤Δv k i ε P k Where Δv k =maximum allowable voltage drop on kth path Spring 2014, Mar 21...

Condition 2: Minimum Width ELEC 7770: Advanced VLSI Design (Agrawal)22 Minimum width allowed by fabrication process: w i =ρ C i s i / x i ≥W Where w i =metal width of ith branch s i =length of ith branch ρ=metal resistivity C i =maximum current in ith branch x i =voltage drop in ith branch W=minimum line width Spring 2014, Mar 21...

Condition 3: Metal Migration ELEC 7770: Advanced VLSI Design (Agrawal)23 Do not exceed maximum current to wire-width ratio: C i / w i = x i /(ρ s i )≤σ i Where w i =metal width of ith branch s i =length of ith branch ρ=metal resistivity C i =maximum current in ith branch x i =voltage drop in ith branch σ i =maximum allowable current density across ith branch Spring 2014, Mar 21...

Decoupling Capacitance ELEC 7770: Advanced VLSI Design (Agrawal)24 +–+– VDD Rg Cd I(t) Spring 2014, Mar 21...

Decoupling Capacitance  Initial charge on Cd, Q 0 = Cd VDD  I(t): current waveform at a node  T: duration of current  Total charge supplied to load: T Q = ∫ I(t) dt 0 ELEC 7770: Advanced VLSI Design (Agrawal)25Spring 2014, Mar 21...

Decoupling Capacitance  Assume that charge is completely supplied by Cd.  Remaining charge on Cd = Cd VDD – Q  Voltage of supply node = VDD – Q/Cd  For a maximum supply noise ΔVDDmax, VDD – (VDD – Q/Cd) ≤ ΔVDDmax OrCd≥Q / ΔVDDmax ELEC 7770: Advanced VLSI Design (Agrawal)26Spring 2014, Mar 21...

A High-Voltage On-Chip Power Distribution Network June 28, 2013 Master’s Thesis Mustafa M. Shihab Auburn University ECE Department June 2013 ELEC 7770: Advanced VLSI Design (Agrawal)27Spring 2014, Mar 21...

On-Chip Power Distribution Network  Power Distribution ‘Grid’: Source: N. Weste et al., CMOS VLSI design: A Circuits and Systems ELEC 7770: Advanced VLSI Design (Agrawal)28Spring 2014, Mar 21...

I 2 R Power Loss 29 Take Away: For a 100 mile long line carrying 1000 MW of 138 kV power loss = 345 kV power loss = 765 kV power loss = 1.1% to 0.5% Source: “American Electric Power Transmission Facts “, ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

I 2 R Power Loss on a Chip 30  I 2 R Loss in On-Chip Power Distribution Network: Increasing Current Density Increasing Wire Resistivity Increasing I 2 R Loss Technology Scaling ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Problem Statement Propose a scheme for delivering power to different parts of a large integrated circuit, such as cores on a system-on-chip (SoC), at a higher than the regular (V DD ) voltage. The increase in voltage will lower the current on the grid, and thereby reduces the I 2 R loss in the on-chip power distribution network. 31 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Typical Power Distribution Network 32 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Proposed Power Distribution Network 33 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Present Distribution Scheme 34  Example: Low-Voltage (V DD ) Power Grid with 9 loads ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Proposed Distribution Scheme 35  Example: High-Voltage (3V) Power Grid with 9 loads ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Result: Low Voltage Distribution 36 Number of Loads Load Power (W) Grid Power (W) Total Power (W) Efficiency (%) Supply Voltage: 1V, Load: 1W Grid Resistances: 0.5 Ω (ITRS 2012) ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Low Voltage PDN Power Transfer 37 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Low Voltage PDN Efficiency 38 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Result: High Voltage Distribution 39 Number of Loads Load Power (W) Grid Power (W) Total Power (W) H-V PDN Efficiency (%) Supply Voltage: 3 V, Load: 1W Grid Resistances: 0.5 Ω (ITRS 2012) DC-DC Converter: LTC 3411-A Linear Technology, 100% Efficiency ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

High Voltage PDN Power Transfer 40 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

High Voltage PDN Efficiency 41 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Result: High Voltage Distribution Number of Loads Load Power (W) Grid Power (W) Total Power (W)Efficiency (%) Supply Voltage: 3 V, Load: 1W Grid Resistances: 0.5 Ω (ITRS 2012) DC-DC Converter: LTC 3411-A Linear Technology, 80% Efficiency ELEC 7770: Advanced VLSI Design (Agrawal)42Spring 2014, Mar 21...

High Voltage PDN Power Transfer 43 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

High Voltage PDN Efficiency 44 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Comparing Grid Power Loss 45 Number of Loads Load Power (W) PDN Grid Power Loss (W) Low- Voltage PDN High-Voltage (100% Eff. Converter) High-Voltage (80% Eff. Converter) ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Comparing Grid Power Loss 46 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Comparing PDN Efficiencies 47 Number of Loads Grid Efficiency (%) Low-Voltage PDN High-Voltage PDN (100% Eff. Converter) High-Voltage PDN (80% Eff. Converter) ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Comparing PDN Efficiencies 48 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Challenges  DC-DC Converter Design:  Efficiency  Power  Area  Output Drive Capacity  Fabrication 49 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

Reported Developments  Input Voltage: 3.3 V Output Voltage: 1.3 V – 1.6 V Output Voltage: 1.3 V – 1.6 V Output Drive Current: 26 mA Output Drive Current: 26 mA Efficiency: 75% - 87% Efficiency: 75% - 87%  Input Voltage: 3.6 V & 5.4 V Output Voltage: 0.9 V Output Voltage: 0.9 V Output Drive Current: 250 mA Output Drive Current: 250 mA Efficiency: 87.8% & 79.6% Efficiency: 87.8% & 79.6% 50 Sources: B. Maity et al., Journal of Low Power Electronics 2012 V. Kursun et al., Multi-voltage CMOS Circuit Design. Wiley, 2006 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

 Have the capability of driving output loads of reasonable size  Have power efficiency of 90% or higher  Meet the tight area requirements of modern high-density ICs  Be fabricated on chip as a part of the SoC  Have ‘regulator’ capability to convert a range of input voltage to the designated output voltage 51 Future Work DC-DC Converters ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

References  D. Chinnery and K. Keutzer, Closing the Power Gap Between ASIC and Custom: Tools and Techniques for Low Power Design. Springer,  M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual for System-on-Chip Design. Springer,  V. Kursun and E. Friedman, Multivoltage CMOS Circuit Design. Wiley,  C. Neau and K. Roy, "Optimal Body Bias Selection for Leakage Improvement and Process Compensation Over Different Technology Generations," Proc. International Symp. Low Power Electronics and Design, 2003, pp  B. C. Paul, A. Agarwal, and K. Roy, "Low-Power Design Techniques for Scaled Technologies,“ Integration, the VLSI Journal, vol. 39, no. 2, pp ,  "Linear Technology: LT3411A DC-DC Converter Demo Nov  M. Pedram and J. M. Rabaey, Power Aware Design Methodologies. Springer,  M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, “On-Chip Power Distribution Grids with Multiple Supply Voltages for High-Performance Integrated Circuits," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 16, no. 7, pp ,  Q. K. Zhu, Power Distribution Network Design for VLSI. Wiley-Interscience, ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...