1. ELEC 7770 Advanced VLSI Design Spring 2016 Power and Ground
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

2. ELEC 7770: Advanced VLSI Design (Agrawal)
References
Q. K. Zhu, Power Distribution Network Design for VLSI, Hoboken, New Jersey: Wiley, 2004.
M. Popovich, A. Mezhiba and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Springer, 2008.
C.-K. Koh, J. Jain and S. F. Cauley, “Synthesis of Clock and Power/Ground Network,” Chapter 13, L.-T. Wang, Y.-W. Chang and K.-T. Cheng (Editors), Electronic Design Automation, Morgan-Kaufmann, pp
J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, Z. Pan, “VLSI On-Chip Power/Ground Network Optimization Considering Decap Leakage Currents,” Proc. Asia and South Pacific Design Automation Conf., 2005 , pp
Decoupling Capacitors,
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

3. ELEC 7770: Advanced VLSI Design (Agrawal)
Supply Voltage
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Supply voltage (V)
Minimum feature size (μm)
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

4. ELEC 7770: Advanced VLSI Design (Agrawal)
Gate Oxide Thickness 60 50 40 30 20 10
Gate oxide thickness (A)
High gate leakage
Minimum feature size (μm)
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

5. ELEC 7770: Advanced VLSI Design (Agrawal)
Power Supply Noise
Transient behavior of supply voltage and ground level.
Caused by transient currents:
Power droop
Ground bounce
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

6. ELEC 7770: Advanced VLSI Design (Agrawal)
Power Supply
V(t)
Gate 2 Rg + – R C R C
VDD
Gate 1
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

7. ELEC 7770: Advanced VLSI Design (Agrawal)
Switching Transients
Only Gate 1 switches (turns on):
V(t) = VDD – Rg VDD exp[– t/{C(R+Rg)}]/(R+Rg)
VDD
VDD[1 – Rg/(R+Rg)]
V(t)
0 time, t
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

8. Multiple Gates Switching
VDD 1 2 3
Gate output voltage
Number of gates switching
many
0 time, t
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

9. ELEC 7770: Advanced VLSI Design (Agrawal)
Decoupling Capacitor
A capacitor to isolate two electrical circuits.
Illustration: An approximate model:
i(t)
VL(t)
t=0 a Rg
VDD = 1
t=0 t + – Rd Cd IL
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

10. Approximate Load Current, IL
0, t < 0 at, t < tp IL = a(2tp – t), t < 2tp 0, t > 2tp
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

11. Transient Load Voltage
VL(t) = 1 – a Rg [ t – Cd Rg (1 – e – t/T) ], 0 < t < tp T = Cd (Rg + Rd)
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

12. Realizing Decoupling Capacitor
VDD
VDD OR
S B D
S B D
GND
GND
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

13. ELEC 7770: Advanced VLSI Design (Agrawal)
Capacitance
Cd = γ×WL×ε×ε0/Tox ≈ 0.26fF, for 70nm BSIM L = 38nm, W = 200nm γ = ε = 4
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

14. ELEC 7770: Advanced VLSI Design (Agrawal)
Leakage Resistance
Igate = α × e – βTox ×W where α and β are technology parameters. Rd = VL(t)/Igate Because V(t) is a function of time, Rd is difficult to estimate. The decoupling capacitance is simulated in spice.
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

15. ELEC 7770: Advanced VLSI Design (Agrawal)
Power-Ground Layout
Solder bump pads
Vss
Vss
Vdd M5
Vdd/Vss supply
Vdd/Vss
equalization M4
Via
Vss
Vdd
Vdd
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

16. ELEC 7770: Advanced VLSI Design (Agrawal)
Power Grid + –
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

17. ELEC 7770: Advanced VLSI Design (Agrawal)
Nodal Analysis V2 g2 g1 g3 Vi V1 V3 g4 Ci
Apply KCL to node i: 4
∑ (Vk – Vi) gk – Ci ∂Vi/∂t = Bi
k=1 Bi V4
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

18. ELEC 7770: Advanced VLSI Design (Agrawal)
Nodal Analysis
G V – C V’ = B
Where G is conductance matrix
V is nodal voltage vector
C is capacitance matrix
B is vector of currents
V(t) is a function of time, V(0) = VDD
B(t) is a function of time, B(0) ≈ 0 or leakage current
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

19. Wire Width Considerations
Increase wire width to reduce resistance:
Control voltage drop for given current
Reduce resistive loss
Reduce wire width to reduce wiring area.
Minimum width restricted to avoid metal migration (reliability consideration).
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

20. A Minimization Problem
Minimize total metal area:
n n
A = ∑ wi si = ∑ | ρ Ci si2 | / xi
i=1 i=1
Where n = number of branches in power network
wi = metal width of ith branch
si = length of ith branch
ρ = metal resistivity
Ci = maximum current in ith branch
xi = voltage drop in ith branch
Subject to several conditions.
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

21. Condition 1: Voltage Drop
Voltage drop on path Pk:
∑ xi ≤ Δvk
i ε Pk
Where Δvk = maximum allowable voltage drop on kth path
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

22. Condition 2: Minimum Width
Minimum width allowed by fabrication process:
wi = ρ Ci si / xi ≥ W
Where wi = metal width of ith branch
si = length of ith branch
ρ = metal resistivity
Ci = maximum current in ith branch
xi = voltage drop in ith branch
W = minimum line width
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

23. Condition 3: Metal Migration
Do not exceed maximum current to wire-width ratio:
Ci / wi = xi /(ρ si) ≤ σi
Where wi = metal width of ith branch
si = length of ith branch
ρ = metal resistivity
Ci = maximum current in ith branch
xi = voltage drop in ith branch
σi = maximum allowable current density across ith branch
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

24. Decoupling CapacitanceRg
VDD + – Cd
I(t)
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

25. Decoupling Capacitance
Initial charge on Cd, Q0 = Cd VDD
I(t): current waveform at a node
T: duration of current
Total charge supplied to load: T
Q = ∫ I(t) dt
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

26. Decoupling Capacitance
Assume that charge is completely supplied by Cd.
Remaining charge on Cd = Cd VDD – Q
Voltage of supply node = VDD – Q/Cd
For a maximum supply noise ΔVDDmax,
VDD – (VDD – Q/Cd) ≤ ΔVDDmax
Or Cd ≥ Q / ΔVDDmax
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

27. A High-Voltage On-Chip Power Distribution Network
Master’s Thesis
Mustafa M. Shihab
Auburn University
ECE Department
June 2013
June 28, 2013
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

28. On-Chip Power Distribution Network
Power Distribution ‘Grid’:
Source: N. Weste et al., CMOS VLSI design: A Circuits and Systems
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

29. ELEC 7770: Advanced VLSI Design (Agrawal)
I2R Power Loss
Take Away: For a 100 mile long line carrying 1000 MW of energy
@ 138 kV power loss = %
@ 345 kV power loss = 4.2%
@ 765 kV power loss = 1.1% to 0.5%
Source:
“American Electric Power Transmission Facts “,
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

30. I2R Power Loss on a Chip
I2R Loss in On-Chip Power Distribution Network:
Increasing Current Density
Increasing Wire Resistivity
Increasing I2R Loss
Technology Scaling
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

31. ELEC 7770: Advanced VLSI Design (Agrawal)
Problem Statement
Propose a scheme for delivering power to different parts of a large integrated circuit, such as cores on a system-on-chip (SoC), at a higher than the regular (VDD) voltage.
The increase in voltage will lower the current on the grid, and thereby reduces the I2R loss in the on-chip power distribution network.
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

32. Typical Power Distribution Network
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

33. ELEC 7770: Advanced VLSI Design (Agrawal)
Proposed Power Distribution Network
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

34. Present Distribution Scheme
Example: Low-Voltage (VDD) Power Grid with 9 loads
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

35. Proposed Distribution Scheme
Example: High-Voltage (3V) Power Grid with 9 loads
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

36. Result: Low Voltage Distribution
Supply Voltage: 1V, Load: 1W
Grid Resistances: 0.5 Ω (ITRS 2012)
Number of Loads
Load Power
(W)
Grid Power
Total Power
Efficiency
(%) 1
0.13
1.13
88.50 4
0.67
4.67
85.65 9
1.69
10.69
84.19 16
3.57
19.57
81.76 25
7.02
32.02
78.08 64
23.76
87.76
72.93
100
49.32
149.32
66.97
256
169.4
425.4
60.18
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

37. Low Voltage PDN Power Transfer
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

38. Low Voltage PDN Efficiency
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

39. Result: High Voltage Distribution
Supply Voltage: 3 V, Load: 1W
Grid Resistances: 0.5 Ω (ITRS 2012)
DC-DC Converter: LTC 3411-A Linear Technology, 100% Efficiency
Number of Loads
Load Power (W)
Grid Power
(W)
Total Power (W)
H-V PDN Efficiency
(%) 1
0.01
1.01
98.58 4
0.07
4.07
98.17 9
0.19
9.19
97.96 16
0.40
16.40
97.58 25
0.78
25.78
96.97 64
2.64
66.64
96.04
100
5.48
105.48
94.80
256
18.82
274.82
93.15
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

40. High Voltage PDN Power Transfer
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

41. High Voltage PDN Efficiency
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

42. Result: High Voltage Distribution
Supply Voltage: 3 V, Load: 1W
Grid Resistances: 0.5 Ω (ITRS 2012)
DC-DC Converter: LTC 3411-A Linear Technology, 80% Efficiency
Number of Loads
Load Power (W)
Grid Power
(W)
Total Power (W)
Efficiency (%) 1
0.02
1.02
98.04 4
0.11
4.11
97.32 9
0.39
9.39
95.85 16
1.21
17.21
92.97 25
2.68
27.68
90.32 64
9.12
73.12
87.53
100
18.97
118.97
84.05
256
63.3
319.3
80.18
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

43. High Voltage PDN Power Transfer
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

44. High Voltage PDN Efficiency
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

45. Comparing Grid Power Loss
Number of Loads
Load Power (W)
PDN Grid Power Loss (W)
Low-Voltage PDN
High-Voltage
(100% Eff. Converter)
(80% Eff. Converter) 1
0.13
0.01
0.02 4
0.67
0.07
0.11 9
1.69
0.19
0.39 16
3.57
0.40
1.21 25
7.02
0.78
2.68 64
23.76
2.64
9.12
100
49.32
5.48
18.97
256
169.40
18.82
63.3
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

46. Comparing Grid Power Loss
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

47. Comparing PDN Efficiency
Number of Loads
Grid Efficiency (%)
Low-Voltage PDN
High-Voltage PDN
(100% Eff. Converter)
(80% Eff. Converter) 1
88.50
98.58
98.04 4
85.65
98.17
97.32 9
84.19
97.96
95.85 16
81.76
97.58
92.97 25
78.08
96.97
90.32 64
72.93
96.04
87.53
100
66.97
94.80
84.05
256
60.18
93.15
80.18
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

48. Comparing PDN Efficiencies
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

49. ELEC 7770: Advanced VLSI Design (Agrawal)
Challenges
DC-DC Converter Design:
Efficiency
Power
Area
Output Drive Capacity
Fabrication
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

50. Reported Developments
Input Voltage: 3.3 V
Output Voltage: 1.3 V – 1.6 V
Output Drive Current: 26 mA
Efficiency: 75% - 87%
Input Voltage: 3.6 V & 5.4 V
Output Voltage: 0.9 V
Output Drive Current: 250 mA
Efficiency: 87.8% & 79.6%
Sources:
B. Maity et al., Journal of Low Power Electronics 2012
V. Kursun et al., Multi-voltage CMOS Circuit Design. Wiley, 2006
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

51. ELEC 7770: Advanced VLSI Design (Agrawal)
Future Work
Have the capability of driving output loads of reasonable size
Have power efficiency of 90% or higher
Meet the tight area requirements of modern high-density ICs
Be fabricated on chip as a part of the SoC
Have ‘regulator’ capability to convert a range of input voltage to the designated output voltage
DC-DC Converters
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)

52. ELEC 7770: Advanced VLSI Design (Agrawal)
References
D. Chinnery and K. Keutzer, Closing the Power Gap Between ASIC and Custom: Tools and Techniques for Low Power Design. Springer, 2007.
M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual for System-on-Chip Design. Springer, 2007.
V. Kursun and E. Friedman, Multivoltage CMOS Circuit Design. Wiley, 2006.
C. Neau and K. Roy, "Optimal Body Bias Selection for Leakage Improvement and Process Compensation Over Different Technology Generations," Proc. International Symp. Low Power Electronics and Design, 2003, pp
B. C. Paul, A. Agarwal, and K. Roy, "Low-Power Design Techniques for Scaled Technologies,“ Integration, the VLSI Journal, vol. 39, no. 2, pp , 2006.
"Linear Technology: LT3411A DC-DC Converter Demo Nov
M. Pedram and J. M. Rabaey, Power Aware Design Methodologies. Springer, 2002.
M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, “On-Chip Power Distribution Grids with Multiple Supply Voltages for High-Performance Integrated Circuits," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 16, no. 7, pp , 2008.
Q. K. Zhu, Power Distribution Network Design for VLSI. Wiley-Interscience, 2004.
Spring 2016, Mar
ELEC 7770: Advanced VLSI Design (Agrawal)