1. Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Low Voltage Low-Power Devices Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.html

2. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 52 Capacitances In Out C1C1 C2C2 V DD GND CWCW Source Drain Source

3. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 53 Miller Capacitance In Out C1C1 C2C2 V DD GND CWCW CMCM

4. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 54 Before Transition In = 0 Out = V DD C1C1 C2C2 V DD GND CWCW CMCM 0 +V DD

5. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 55 After Transition In Out C1C1 C2C2 V DD GND CWCW CMCM 0 +V DD Energy from supply = 2 C M V DD 2 Effective capacitance = 2 C M from pull-up devices of previous gate

6. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 56 Capacitances in MOSFET SourceDrain Gate oxide Gate Bulk CsCs CdCd CgCg C gd C gs

7. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 57 Bulk nMOSFET n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon

8. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 58 Gate Capacitance C g = C ox WL = C 0, intrinsic cap. C g = C permicron W ε ox C permicron =C ox L=── L t ox where ε ox = 3.9ε 0 for Silicon dioxide = 3.9×8.85×10 -14 F/cm

9. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 59 Approx. Intrinsic Capacitances Capacitance Region of operation CutoffLinearSaturation Cgb C0C0C0C000 Cgs0 C 0 /2 2/3 C 0 Cgd0 C 0 /2 0 Cg = Cgs+Cgd+Cgb C0C0C0C0 C0C0C0C0 2/3 C 0 Weste and Harris, CMOS VLSI Design, Addison-Wesley, 2005, p. 78.

10. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 510 Low-Power Transistors Device scaling to reduce capacitance and voltage. Device scaling to reduce capacitance and voltage. Body bias to reduce threshold voltage and leakage. Body bias to reduce threshold voltage and leakage. Multiple threshold CMOS (MTCMOS). Multiple threshold CMOS (MTCMOS). Silicon on insulator (SOI) Silicon on insulator (SOI)

11. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 511 Device Scaling Reduced dimensions Reduced dimensions Reduce supply voltage Reduce supply voltage Reduce capacitances Reduce capacitances Reduce delay Reduce delay Increase leakage due to reduced V DD / V th Increase leakage due to reduced V DD / V th

12. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 512 A Simplistic View Assume: Assume: Dynamic power dominates Dynamic power dominates Power reduces as square of supply voltage; should reduce with device scaling Power reduces as square of supply voltage; should reduce with device scaling Power reduced linearly with capacitance; should reduce with device scaling Power reduced linearly with capacitance; should reduce with device scaling Delay is proportional to RC time constant; R is constant with scaling, RC should reduce Delay is proportional to RC time constant; R is constant with scaling, RC should reduce Power reduces with scaling Power reduces with scaling

13. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 513 Simplistic View (Continued) What if voltage is further reduced below the constant electric field value? What if voltage is further reduced below the constant electric field value? Will power continue to reduce? Yes. Will power continue to reduce? Yes. Since RC is independent of voltage, can clock rate remain unchanged? Since RC is independent of voltage, can clock rate remain unchanged? Answer to last question: Answer to last question: Yes, if threshold voltage was zero. Yes, if threshold voltage was zero. No, in reality. Because relatively higher threshold voltage will delay the beginning of capacitor charging/discharging. No, in reality. Because relatively higher threshold voltage will delay the beginning of capacitor charging/discharging.

14. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 514 Consider Delay of Inverter In Out V DD GND C R t B Charging of C begins

15. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 515 Idealized Input and Output t f V th t B t B 0.5V DD V DD time 0.69CR INPUT OUTPUT Gate delay t B = t f V th /V DD 0.5V DD

16. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 516 Gate Delay For V DD >V th Gate delay=(t f V th /V DD ) + 0.69RC – 0.5 t f =t f (V th /V DD – 0.5 ) + 0.69RC For V DD ≤V th Gate delay=∞

17. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 517 Approx. Gate Delay vs. V DD 0.69RC 0.5t f 0 1 2 3 4 5 Gate delay V DD /V th

18. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 518 Power - Delay vs. V DD 0.69RC 0.5t f 0 1 2 3 4 5 Gate delay V DD /V th Power With leakage ~CV DD 2

19. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 519 Optimum Threshold Voltage V DD / V th 01234560123456 Delay or Energy-delay product Delay Energy-delay product V th = 0.7V V th = 0.3V J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston, Springer, 1996, p. 26. V th can be changed by varying doping level, oxide thickness and body bias.

20. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 520 Low-Voltage Inverter Assumed always in saturation. Assumed always in saturation. Modeled as ideal current source. Modeled as ideal current source. CLCL ViVi VoVo CLCL V i = V DD VoVo K(V DD –V thn ) K(V DD + V thp ) CLCL V i = 0 VoVo K(V DD –V thn ) K(V DD + V thp ) V DD

21. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 521 Power Supply Scaling V o Volts 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.2 0.40.6 0.8 1.0 1.0 0.8 0.6 0.4 0.2 0.0 I DD mA V i Volts V DD = 1V V DD = 0.5V V th ≈ 0.35V J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, IEEE Press and Wiley-Interscience, 2004, p. 116.

22. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 522 Bulk nMOSFET n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon V gs V gd V ds + + +

23. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 523 Transistor in Cut-Off State +-+- V g < 0 - - - - - - - - - + + + + + + + + + + + + + Polysilicon gate SiO 2 p-type body

24. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 524 Threshold Voltage, V th +-+- 0 < V g < V th + + + + + + + + + + + + + + + + + + Depletion region Polysilicon gate SiO 2 p-type body +-+- V g > V th + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - Depletion region + + + + + + + + + + + + + Polysilicon gate SiO 2 p-type body V th is a function of: Dopant concentration, Thickness of oxide

25. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 525 Cutoff: I ds = 0 n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon V gs V gd V ds = 0 + + + = 0

26. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 526 Linear: I ds = 0 n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon V gs V gd V ds = 0 + + + > V th = V gs - - -

27. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 527 Linear: I ds Increases with V ds n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon V gs V gd 0 < V ds < V gs -V th + + + > V th V gs > V gd > V th - - -

28. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 528 Saturation: I ds Independent of V ds n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon V gs V gd 0 V gs - V th + + + > V th V gd < V th - - -

29. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 529 α-Power Law Model α-Power Law Model V gs > V th and V ds > V dsat = V gs – V th (Saturation region): β I ds =P c ─ (V gs – V th ) α 2 whereβ=μC ox W/L, μ = mobility For fully ON transistor, V gs = V ds = V DD : β I dsat =P c ─ (V DD – V th ) α 2 T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas,” IEEE J. Solid State Circuits, vol. 25, no. 2, pp. 584-594, 1990.

30. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 530 α-Power Law Model (Cont.) V gs = 1.8V Shockley α-power law Simulation V ds I ds (μA) 0 0.3 0.6 0.9 1.2 1.5 1.8 400 300 200 100 0 I dsat

31. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 531 α-Power Law Model (Cont.) 0V gs < V th cutoff I ds =I dsat × V ds /V dsat V ds < V dsat linear I dsat V ds > V dsat saturation V dsat =P v (V gs – V th ) α/2

32. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 532 α-Power Law Model (Cont.) α = 2, for long channel devices or low V DD α = 2, for long channel devices or low V DD α ~ 1, for short channel devices α ~ 1, for short channel devices

33. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 533 Power and Delay Power=CV DD 2 CV DD 1 1 Inverter delay=──── (─── + ─── ) 4 I dsatn I dsatp KV DD =─────── (V DD – V th ) α

34. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 534 Power-Delay Product V DD 3 Power × Delay=constant ×─────── (V DD – V th ) α 0.6V1.8V3.0V V DD Power Delay

35. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 535 Optimum Threshold Voltage For minimum power-delay product: 3V th V DD =─── 3 – α For long channel devices, α = 2, V DD = 3V th For very short channel devices, α = 1, V DD = 1.5V th

36. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 536 Leakage IGIG IDID I sub I PT I GIDL n+ Ground V DD R

37. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 537 Leakage Current Components Subthreshold conduction, I sub Subthreshold conduction, I sub Reverse bias pn junction conduction, I D Reverse bias pn junction conduction, I D Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap Drain source punchthrough, I PT due to short channel and high drain-source voltage Drain source punchthrough, I PT due to short channel and high drain-source voltage Gate tunneling, I G through thin oxide Gate tunneling, I G through thin oxide

38. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 538 Subthreshold Leakage V gs – V th I sub =I 0 exp( ───── ), where v T = kT/q = 26 mV n v T at 300K 0 0.3 0.6 0.9 1.2 1.5 1.8 V V gs I ds 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA V th Subthreshold region Saturation region

39. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 539 Normal CMOS Inverter Polysilicon (input) SiO 2 p+ n+ p+ n+ n-well p-substrate (bulk) metal 1 V DD GND output input output VDD GND o

40. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 540 Leakage Reduction by Body Bias Polysilicon (input) SiO 2 p+ n+ p+ n+ n-well p-substrate (bulk) metal 1 V DD GND output input output V BBp V DD GND V BBn V BBp o

41. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 541 Body Bias, V BBn +-+- 0 < V g < V th + + + + + + + + + + + + + + + + + + Depletion region Polysilicon gate SiO 2 p-type body +-+- V g < 0 - - - - - - - - - + + + + + + + + + + + + + Polysilicon gate SiO 2 p-type body V t is a function of: Dopant concentration, Thickness of oxide

42. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 542 Further on Body Bias Large body bias can increase gate leakage (I G ) via tunneling through oxide. Large body bias can increase gate leakage (I G ) via tunneling through oxide. Body bias is kept less than 0.5V. Body bias is kept less than 0.5V. For V DD = 1.8V For V DD = 1.8V V BBn = - 0.4V V BBn = - 0.4V V BBp = 2.2V V BBp = 2.2V

43. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 543 Summary Device scaling down reduces supply voltage Device scaling down reduces supply voltage Reduced power Increases delay Optimum power-delay product by scaling down threshold voltage Optimum power-delay product by scaling down threshold voltage Threshold voltage reduction increases subthreshold leakage power Use body bias to reduce subthreshold leakage Body bias may increase gate leakage