NanoFab Trainer Nick Reeder June 28, 2012.

Slides:

Advertisements

Similar presentations

Malaviya National Institute of Technology

Advertisements

FABRICATION PROCESSES

ENGR-45_Lec-06_Diffusion_Fick-1.ppt 1 Bruce Mayer, PE Engineering-45: Materials of Engineering Bruce Mayer, PE Registered Electrical.

Process Flow : Overhead and Cross Section Views ( Diagrams courtesy of Mr. Bryant Colwill ) Grey=Si, Blue=Silicon Dioxide, Red=Photoresist, Purple= Phosphorus.

CMOS Fabrication EMT 251.

Simplified Example of a LOCOS Fabrication Process

CMOS Process at a Glance

VLSI Design Lecture 2: Basic Fabrication Steps and Layout

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.

1 Microelectronics Processing Course - J. Salzman - Jan Microelectronics Processing Oxidation.

Overview of Nanofabrication Techniques Experimental Methods Club Monday, July 7, 2014 Evan Miyazono.

Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.

Introduction to CMOS VLSI Design Lecture 0: Introduction

Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

1 N/P-Channel MOSFET Fabrication By Assoc. Prof Dr. Uda Hashim School of Microelectronic Enginnering KUKUM FOX N-Well Arsenic Implant LDD As+ S/D Implant.

The Physical Structure (NMOS)

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,

CSCE 613: Fundamentals of VLSI Chip Design Instructor: Jason D. Bakos.

YoHan Kim  Thin Film  Layer of material ranging from fractions of nanometer to several micro meters in thickness  Thin Film Process 

Device Fabrication Example

Introduction Integrated circuits: many transistors on one chip.

ECE685 Nanoelectronics – Semiconductor Devices Lecture given by Qiliang Li.

Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.

Katedra Experimentálnej Fyziky Bipolar technology - the size of bipolar transistors must be reduced to meet the high-density requirement Figure illustrates.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #7. Etching  Introduction  Etching  Wet Etching  Dry Etching  Plasma Etching  Wet vs. Dry Etching  Physical.

ISAT 436 Micro-/Nanofabrication and Applications MOS Transistor Fabrication David J. Lawrence Spring 2001.

Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.

CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.

Fabrication of Active Matrix (STEM) Detectors

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #2. Chip Fabrication  Silicon Ingots  Wafers  Chip Fabrication Steps (FEOL, BEOL)  Processing Categories 

1. A clean single crystal silicon (Si) wafer which is doped n-type (ColumnV elements of the periodic table). MOS devices are typically fabricated on a,

SEMINAR ON IC FABRICATION MD.ASLAM ADM NO:05-125,ETC/2008.

I.C. Technology Processing Course Trinity College Dublin.

SEMINAR PRESENTATION ON IC FABRICATION PROCESS

Virtual NanoFab A Silicon NanoFabrication Trainer

Feb 2007Stith1 Semiconductors Material, Components, and Manufacture Joseph Stith February 2007.

Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.

Introduction to Wafer fabrication Process

Top Down Manufacturing

By: Joaquin Gabriels November 24 th,  Overview of CMOS  CMOS Fabrication Process Overview  CMOS Fabrication Process  Problems with Current CMOS.

Top Down Method Etch Processes

Introduction EE1411 Manufacturing Process. EE1412 What is a Semiconductor? Low resistivity => “conductor” High resistivity => “insulator” Intermediate.

Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.

IC Processing. Initial Steps: Forming an active region Si 3 N 4 is etched away using an F-plasma: Si3dN4 + 12F → 3SiF 4 + 2N 2 Or removed in hot.

ISAT 436 Micro-/Nanofabrication and Applications Photolithography David J. Lawrence Spring 2004.

CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.

NanoFab Simulator Update Nick Reeder, May 17, 2012.

Substitute beer and pizza?. Basic Silicon Solar Cell as fabricated in Cameron With Schematic.

©2008 R. Gupta, UCSD COSMOS Summer 2008 Chips and Chip Making Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.

NanoFab Trainer Update Nick Reeder, March 1, 2013.

Fundamentals of Semiconductor Physics 万歆 Zhejiang Institute of Modern Physics Fall 2006.

 Refers to techniques for fabrication of 3D structures on the micrometer scale  Most methods use silicon as substrate material  Some of process involved.

CMOS VLSI Fabrication.

CMOS FABRICATION.

Side ViewTop View Beginning from a silicon wafer.

1 Device Fabrication And Diffusion Overview 5 and 8 February 2016 Silicon Wafer Production-Refer to Chapter “0” Prologue Raw material ― Polysilicon nuggets.

Patterning - Photolithography

CMOS Fabrication EMT 251.

IC Manufactured Done by: Engineer Ahmad Haitham.

Basic Planar Processes

CMOS Fabrication CMOS transistors are fabricated on silicon wafer

Manufacturing Process I

NanoFab Simulator Update

VLSI System Design LEC3.1 CMOS FABRICATION REVIEW

Silicon Wafer cm (5’’- 8’’) mm

Manufacturing Process I

NanoFab Trainer Update

Manufacturing Process I

CSE 87 Fall 2007 Chips and Chip Making

Presentation transcript:

NanoFab Trainer Nick Reeder June 28, 2012

NanoFab Trainer Educational tool that lets user see the results of performing sequences of basic nanofabrication operations on a silicon (Si) wafer. Runs under Windows operating system. Written in LabVIEW 2009; requires LabVIEW 2009 Run-Time Engine ( free download at ).

User Operations Ion implantation (“doping”) Thermal oxidation Photolithography Depositing layers of material Removing material

Ion Implantation Modifies the electrical characteristics of the silicon wafer. Such modification is the key technique underlying the operation of semiconductor devices (diodes, transistors, thyristors). Implanting boron results in “p-type” doping. Implanting phosphorus results in “n-type” doping.

Example: Fabricating a MOSFET MOSFET = Metal-oxide-semiconductor field effect transistor

Thermal oxidation Grows a layer of silicon dioxide (SiO 2 ) on the wafer surface. Key properties of SiO 2 : – Impervious to ion implantation. – Can be etched away by immersion in hydrofluoric acid (HF), which does not etch silicon.

Photolithography Steps in photolithography: – Spin-coat photoresist. – Create and place mask. Mask defines which areas will be exposed to UV light and which areas will be shaded. – Expose with UV light. – “Develop” the photoresist: UV-exposed areas are removed, while shaded areas remain. Wikipedia

Depositing Layers Methods of depositing layers of material – Electron-beam evaporation – Chemical vapor deposition (CVD) – Sputtering The materials deposited may be metals, dielectrics, or semiconductors.

Removing material Methods of removing material – Wet etching Low-tech Immerse wafer in a bath of liquid acid or solvent – Dry etching High-tech Expose wafer to plasma beam

Other Features of Trainer Maintains history of user operations. Will track cost, time, and quality of user operations. “Tutorial” page will provide photos and videos of operations being performed in the lab, along with text explaining theory.