Presentation is loading. Please wait.

Presentation is loading. Please wait.

1 N/P-Channel MOSFET Fabrication By Assoc. Prof Dr. Uda Hashim School of Microelectronic Enginnering KUKUM FOX N-Well Arsenic Implant LDD As+ S/D Implant.

Published bySamantha Bruce Modified over 8 years ago

Similar presentations

Presentation on theme: "1 N/P-Channel MOSFET Fabrication By Assoc. Prof Dr. Uda Hashim School of Microelectronic Enginnering KUKUM FOX N-Well Arsenic Implant LDD As+ S/D Implant."— Presentation transcript:

1 1 N/P-Channel MOSFET Fabrication By Assoc. Prof Dr. Uda Hashim School of Microelectronic Enginnering KUKUM FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Planarisation Metal 2 Passivation P+ Substrate Spacer Test Insert and Scribe-line

2 2 The making of transistor Circuit design Mask/layout design Mask making and artwork Fabrication process Device testing – for parametric and functional test Packaging and Reliability Test

3 3 Mask Design

4 4 MOSFET Masking Step Mask 1: Source Drain Mask Mask 2: Gate Mask Mask 3: Contact mask Mask 4: Metallization Mask

5 5 Introduction Mask design is very important before fabrication process can be done. Design rules must be followed to prevent defect in the process. In this design, gate length is varied from 30um, 50um, 100um, 150um, 200um and 300um. Different gate length will have different gate mask and different distance from source to drain. The smaller the gate size, the better the transistor in speed.

6 6 Circuit, layout and cross section of NMOS transistor In NMOS design, NMOS circuit is transferred to layout design. Then, mask can be design to fabricate NMOS transistor.

7 7 MASK 1: Source Drain Mask Mask 1 is used to control the heavily phosphorus doped and create the source and drain region of the n_channel device. Layout 1: Source and Drain

8 8 Mask 2: Gate Mask Mask 2 is used to remove the thick oxide layer and grow a very high quality of thin oxide. Layout 2: Layout 1 and gate

9 9 Mask 3: Contact mask Mask 3 is used to pattern the contact holes. Etching will open the holes. Layout 3: Layout 2 and contact

10 10 Mask 4: Metallization Mask Mask 4 is used to pattern the connection. The uncovered Aluminum film will be removed during etching process. Layout 4: Layout 3 and metallization

11 11 Mask Design using AutoCAD

12 12 Mask Design Step Step 1: Set frame and wafer size dimension Step 2:Design alignment mark Step 3:Design source and drain mask (Mask 1) block and duplicate to the whole wafer. Step 4: Design gate mask (Mask 2) block and duplicate to the whole wafer. Then, inverse the alignment mark to change the polarity.

13 13 Step 5: Design contact mask (Mask 3) block and duplicate to the whole wafer. Step 6: Design Metallization mask (Mask 4) block and duplicate to the whole mask. Step 7: Print on transparency film using high resolution printer.

14 14 Step 1: Set frame and wafer size dimension The frame size is set to 20” x 12” (A4 paper size). The wafer diameter is set to 4” and the wafer block is set to 6” x 6”. Then the design unit is set to millimeter or micron depend on the designer’s convenience.

15 15 Step 2: Alignment Mark design Alignment mark is used to align wafer between layer to layer during the fabrication process. First, design the alignment block. Then, design the cross an insert it inside the block.

16 16 Step 3: Design source and drain mask First, design the mask block. Then, design the source and drain region which is uncovered and designed with desired dimension. At this mask, the polarity of the alignment block is reversed. The cross is open and the block is opaque.

17 17 Step 4: Design gate mask The red block is the gate mask, it is drawn before the white area. The white area on the red layer is the gate region. Maintain the mask design

18 18 Step 5: Design contact mask The brown block is the gate mask. The white rectangle is the contact region. Maintain the mask design

19 19 Step 6: Design metallization mask The Metallization mask is used for routing purposes. The unprotected region will be etched away whereby the exposed Aluminum area will be removed. Maintain the mask design

20 20 Q & A

21 21 Transistor Fabrication (Step by Step Process)

22 22 n-channel MOSFET Fabrication The device fabrication steps are shown for n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (FET). All photolithography processes are shown by means of animation. The steps shown here are the most detailed and serve as basis for the next few applets showing the device fabrication. A lightly doped p-type Si wafer

23 23 For NMOS process, the starting material is a P-type lightly doped, -oriented, polished silicon wafer. The first step is to form the SiO2 layer(0.5 - 1um thick) by thermal oxidation. The oxidation temperature is generally in the range of 900 - 1200 degree C, and the typical gas flow rate is about 1cm/s. Oxide Grown

24 24 Photoresist Applied Following oxidation, several drops of positive Photoresist(e.g. Shipley S1818) are dropped on the wafer. The wafer is spun at about 3000rpm to be uniformly spread out.After the spinning step, the wafer is given a pre-exposure baking (80 - 100 degree C) to remove the solvent from the PR film and improve adhesion to the substrate.

25 25 PR Developed Third step is to define the active area (Drain and Source regions) by photolithography.The PR layer not covered by the mask undergoes a chemical change by UV light and is removed by the spraying the wafer with the developing solution(e.g. Shipley MF319). The final remaining PR is a copy of the pattern on the mask. Finally,the wafer is rinsed and spin-dried, and then baked again so that the PR can resist the strong acid used to etch the exposed oxide layer.

26 26 Oxdie Etched For SiO2 etching, HydroFluoric(HF) acid is usually used because it attacks oxide, but not silicon or PR. Therefore, the HydroFluoric(HF) acid etches away the oxide in the openings in the PR, and stops at the silicon surface.

27 27 PR Removed After SiO2 etching, PR is stripped by using either a solvent (Aceton) or a plasma oxidation, leaving behind an insulator pattern that is the same as the opaque image on the mask.

28 28 Phosphorus Diffused After stripping the PR,a two-step diffusion process is used to form drain and source regions, in which Phosphorus predeposition is first formed under a Constant-Surface-Concentration Condition(CSCC) and then is followed by a drive-in diffusion under a Constant-Total-Dopant Condition(CTDC). Finally, a thin layer of Phosphosilicate Glass on the wafer is removed by HF

29 29 Field Oxide Grown After the forming the drain and source regions, additional oxide layer is grown from thermal oxidation as before. The Phosphorus spreads out by diffusion during this furnace operation, but the concentration are still much higher than that of the substrate doping.

30 30 PR Applied The second photolithography process is done to remove the oxide, defining a gate region. The same procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing - > Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

31 31 PR Developed The second photolithography process is done to remove the oxide, defining a gate region. The same procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing - > Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

32 32 Oxide Etched The second photolithography process is done to remove the oxide, defining a gate region. The same procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing - > Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

33 33 PR Stripped The second photolithography process is done to remove the oxide, defining a gate region. The same procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing - > Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

34 34 Gate Oxide Grown After the second photolithography, a very thin gate oxide layer(a few hundred angstroms) is grown by thermal oxidation.

35 35 PR Applied The third photolithography process is done to remove the oxide, defining contact holes. The same procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

36 36 PR Developed The third photolithography process is done to remove the oxide, defining contact holes. The same procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

37 37 Oxide Etched The third photolithography process is done to remove the oxide, defining contact holes. The same procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

38 38 PR Removed The third photolithography process is done to remove the oxide, defining contact holes. The same procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

39 39 Aluminium Film Deposited A metal such as Aluminum is then evaporated on the whole substrate surface(a few thousand angstrom thick) under high-vacuum condition.This method is attractive because it is simple and inexpensive and produces no ionizing radiation.The Al layer will form electrical contacts later.

40 40 PR Applied The final lithography process is done to remove the Al-layer, defining a contact pattern. The same procedure( PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure ->PR Developing->Rinsing and Drying->Post-Baking ->Aluminum Etching) as in lithography #1 is used.

41 41 PR Developed The final lithography process is done to remove the Al-layer, defining a contact pattern. The same procedure( PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure ->PR Developing->Rinsing and Drying->Post-Baking ->Aluminum Etching) as in lithography #1 is used.

42 42 Aluminium Interconnect Etched The final lithography process is done to remove the Al-layer, defining a contact pattern. The same procedure( PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure ->PR Developing->Rinsing and Drying->Post-Baking ->Aluminum Etching) as in lithography #1 is used.

43 43 Completion of NMOS Fabrication After the final PR stripping, all the NMOS fabrication steps are completed.

44 44 Runcard preparation Process runcard Measurement sheet Rework sheet Equipments list Consumables list Design specification Complete Mask Design

45 45 Thanks

Download ppt "1 N/P-Channel MOSFET Fabrication By Assoc. Prof Dr. Uda Hashim School of Microelectronic Enginnering KUKUM FOX N-Well Arsenic Implant LDD As+ S/D Implant."

Similar presentations

Malaviya National Institute of Technology

Malaviya National Institute of Technology
Process Flow : Overhead and Cross Section Views ( Diagrams courtesy of Mr. Bryant Colwill ) Grey=Si, Blue=Silicon Dioxide, Red=Photoresist, Purple= Phosphorus.

Process Flow : Overhead and Cross Section Views ( Diagrams courtesy of Mr. Bryant Colwill ) Grey=Si, Blue=Silicon Dioxide, Red=Photoresist, Purple= Phosphorus.
CMOS Fabrication EMT 251.

CMOS Fabrication EMT 251.
Lecture 0: Introduction

Lecture 0: Introduction
Simplified Example of a LOCOS Fabrication Process

Simplified Example of a LOCOS Fabrication Process
CMOS Process at a Glance

CMOS Process at a Glance
VLSI Design Lecture 2: Basic Fabrication Steps and Layout

VLSI Design Lecture 2: Basic Fabrication Steps and Layout
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.
Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask.

Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask.
Introduction to CMOS VLSI Design Lecture 0: Introduction

Introduction to CMOS VLSI Design Lecture 0: Introduction
Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.

Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.
The Physical Structure (NMOS)

The Physical Structure (NMOS)
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,
Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.

Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.
Device Fabrication Example

Device Fabrication Example
Introduction Integrated circuits: many transistors on one chip.

Introduction Integrated circuits: many transistors on one chip.
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.
CMOS Process Integration ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May March 25, 2004.

CMOS Process Integration ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May March 25, 2004.
Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.

Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #7. Etching  Introduction  Etching  Wet Etching  Dry Etching  Plasma Etching  Wet vs. Dry Etching  Physical.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #7. Etching  Introduction  Etching  Wet Etching  Dry Etching  Plasma Etching  Wet vs. Dry Etching  Physical.

Similar presentations

Ads by Google