Leo Greiner PIXEL Hardware meeting HFT PIXEL detector LVDS Data Path Testing

Leo Greiner PIXEL Hardware meeting Outline Review of RDO design. LVDS Data Path test design Status For more information, please see:

Leo Greiner PIXEL Hardware meeting Phase-1 Sensor characteristics 640 x 640 array – 30 micron pixels On-chip CDS and discriminators 4 LVDS outputs / sensor Rolling shutter readout – binary digital data per pixel 640 microsecond integration time 160 MHz LVDS RDO clock speed (this is configurable) The Ultimate sensor will have on chip zero-suppression and 1 output / sensor. The readout clock can be slower than the 160 MHz required for the Phase-1.

Leo Greiner PIXEL Hardware meeting RDO System Design – System Blocks This is a highly parallel system – a schematic representation is shown below.

Leo Greiner PIXEL Hardware meeting m – Low mass twisted pair 6 m - twisted pair RDO System Design – Physical Layout Sensors, Ladders, Carriers (interaction point) LU Protected Regulators, Mass cable termination RDO Boards DAQ PCs Magnet Pole Face (Low Rad Area) DAQ Room Power Supplies Platform 30 m 100 m - Fiber optic cables

Leo Greiner PIXEL Hardware meeting Detailed RDO System Structure – Sensors and Cables Early prototype cable with 40 differential pair output, clock and control routed under sensor area. 4 LVDS outputs / sensor Cable 4 layer micron thickness Aluminum Conductor Radiation Length ~ 0.1 % 40 LVDS pair signal traces Clock, JTAG, sync, marker Fine twisted pair cables 125 micron diameter wire Soldered directly to cable Low stiffness / mass

Leo Greiner PIXEL Hardware meeting Detailed RDO System Structure – LU Protection and Mass Termination 1 Main Board per carrier 10 carriers in the PIXEL detector

Leo Greiner PIXEL Hardware meeting Detailed RDO System Structure – RDO Board(s) New motherboard Two board System – Virtex-5 Development board mated to a new HFT motherboard Xilinx Virtex-5 Development Board Digital I/O LVDS Drivers 4 X >80 MHz ADCs PMC connectors for SIU Cypress USB chipset SODIMM Memory slot Serial interface Trigger / Control input FF1760 Package 800 – 1200 I/O pins 4.6 – 10.4 Mb block RAM 550 MHz internal clock Note – This board is designed for development and testing. Not all features will be loaded for production.

Leo Greiner PIXEL Hardware meeting Data Path LVDS Test Block Diagram

Leo Greiner PIXEL Hardware meeting Testing Plan Bit Error Rate and Eye Pattern Plots for combinations of: 1.Different cable types from the Mass-termination board to the V5 interface board. 2.Different cable lengths from the Mass-termination board to the V5 interface board. 3.Range of clock RDO frequencies including pseudo random data and clock data. 4.Hardware configuration either straight path through Mass- termination board or through buffers.

Leo Greiner PIXEL Hardware meeting Status Virtex-5 Development Board – in hand and ready for testing. Ladder test board – Layout completed. Soliciting quotations for PCB fabrication. Mass-termination board – in Layout. V5 interface board – Schematic complete. Ready for layout. We anticipate being ready to begin testing in mid January.

Leo Greiner PIXEL Hardware meeting fin

Leo Greiner PIXEL Hardware meeting Detailed System Structure – RDO Functional Data Path – Phase 1

Leo Greiner PIXEL Hardware meeting Data Rates - Parameters Rates as per Jim Thomas, L = 3 x for Phase-1, L = 8 x for Ultimate. 2.5 hits / cluster. 1 kHz average event rate. 10 inner ladders, 30 outer ladders. Factor of 1.6 for event format overhead (can be lowered). No run length encoding R = 2.5R = us 640 us Hits / Sensor at L = 8 x Integration Time Radius

Leo Greiner PIXEL Hardware meeting Data Rates Ultimate => 49.7 MB / s raw addresses. => 79.5 MB / s data rate. Phase–1 => 59.6 MB / s raw addresses => 95.4 MB / s data rate. The dead-time is primarily limited by the number of externally allocated readout buffers!