1. LBNL Eric Anderssen, Leo Greiner, Thorsten Stezelberger, Joe Silber, Xiangming Sun, Michal Szelezniak, Chinh Vu, Howard Wieman UTA Jerry Hoffman, Jo Schambach IPHC Michal Szelezniak on behalf of the PICSEL group Development of the STAR PXL detector based on CMOS sensors 5 – 7 June, IPN LyonJournées VLSI - FPGA - PCB de l'IN2P3

2. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 2 2 Michal Szelezniak STAR Heavy Flavor Tracker (HFT) upgrade PXL detector characteristics PXL readout system CMOS sensors for PXL Building ladders Probe tests Readout cable development Ladder prototypes Summary Outline

3. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 3 3 Michal Szelezniak STAR Heavy Flavor Tracker (HFT) Upgrade The HFT is a tracking upgrade to the STAR detector to identify mid rapidity Charm and Beauty mesons and baryons through direct reconstruction and measurement of the displaced vertex with excellent pointing resolution. Graded resolution: TPC→SSD → IST → PXL ~1mm ↘ ~300µm ↘ ~250µm ↘ <30µm TPC – Time Projection Chamber (main detector in STAR) HFT – Heavy Flavor Tracker SSD – Silicon Strip Detector IST – Inner Silicon Tracker PXL – Pixel Detector (PIXEL)

4. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 4 4 Michal Szelezniak PXL Detector Characteristics Pointing resolution(12  19GeV/p  c)  m LayersLayer 1 at 2.5 cm radius Layer 2 at 8 cm radius Pixel size20.7  m X 20.7  m Hit resolution6  m Position stability6  m rms (20  m envelope) Radiation length per layerX/X 0 = 0.37% Number of pixels356 M Integration time (affects pileup) 185.6  s Radiation requirement20 to 90 kRad 2*10 11 to 10 12 1MeV n eq/cm 2 Rapid detector replacement< 8 Hours 356 M pixels on ~0.16 m 2 of Silicon

5. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 5 5 Michal Szelezniak Mechanical support with kinematic mounts (insertion side) Insertion from one side 2 layers 5 sectors / half (10 sectors total) 4 ladders/sector Aluminum conductor Ladder Flex Cable Ladder with 10 MAPS sensors (~ 2×2 cm each) carbon fiber sector tubes (~ 200µm thick) 20 cm PXL detector mechanical design

6. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 6 6 Michal Szelezniak PIXEL Mechanical Support A well controlled method for installation of the pixel detector has been developed with emphasis on ease of operation and avoidance of detector risk Insertion mechanism to guide detector around beam pipe and beam pipe support uses track and carriage with hinge and cam to guide into final docking position defined by locking kinematic mounts other requirements: Fast detector replacement capabilities Air cooling Mechanical stability within a 20 μm window is required.

7. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 7 7 Michal Szelezniak PIXEL Thermal Studies - Analysis and Testing - Silicon power: 100 raised to 170 mW/cm 2 (~ power of sunlight) 350 W total in the low mass region (Si + drivers) CFD computational fluid dynamics An air-flow based cooling system has been chosen for PIXEL to minimize material budget. Detector mockup to study cooling efficiency low mass region The large CTE difference between silicon and kapton is a potential source of thermal induced deformation.

8. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 8 8 Michal Szelezniak PXL Detector Basic Unit (RDO) (1 st gen) 2 m (42 AWG TP) 6 m (24 AWG TP) 100 m (fiber optic) Highly parallel system 4 ladders per sector 1 Mass Termination Board (MTB) per sector 1 sector per RDO board 10 RDO boards in the PXL system RDO motherboard w/ Xilinx FPGA RDO PC with DDL link to RDO board Mass Termination Board + latch-up protected power daughter-card Clk, config, power, data 4×10×2×160 MHz Clk, config, data PXL built events  trigger @ 1 kHz (2.1 Gb/s) (Complete system ~200 MB/s)

9. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 9 9 Michal Szelezniak Production Prototype RDO board SIU Daughter Card (ADC,SRAM) USB JTAG VME P1 Ladder Data Connectors (VHDCI) Xilinx Virtex-6 FPGA

10. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 10 Michal Szelezniak CMOS Sensors for PXL Pixel Sensors CDS ADC Data sparsification readout to DAQ analog signals Complementary detector readout MimoSTAR sensors 4 ms integration time PXL production sensors (Ultimate) < 200 μs integration time analog digital digital signals Disc. CDS Phase-1 sensors 640 μs integration time Sensor and RDO Development Path MAPS sensors for PXL are developed at IPHC, Strasbourg 3 generation program with highly coupled sensor and readout development 1 2 3

11. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 11 Michal Szelezniak PXL production sensor (Ultimate) Reticle size (~ 4 cm²) Pixel pitch 20.7 μm 960 col x 928 rows  890 k pixels Vdd: 3.3 or 3.0 V Power consumption ~150 mW/cm² Integration time 185.6 μs on-chip zero suppression 2 LVDS data outputs @ 160 MHz

12. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 12 Michal Szelezniak Probe Tests Testing diced and thinned sensors to meet yield requirements for ladder assembly Vacuum chuck for probe testing 50 μm thick MAPS Sensors designed with dedicated probe pads in the sensor pad ring Automated test system allows for a qualitative analysis of probed sensors Testing current draw, JTAG functionality Sensor characterization (noise, FPN), including identification of dead/stuck pixels Prototype probe card (tested with a wire bonded sensor)

13. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 13 Michal Szelezniak 2 layer Al conductor cable with vias in low mass region 0.004” (100 µm) traces and 0.004” (100 µm) spaces 70% fill factor Conductor thickness in low mass region is 21 µm (Cu) or 32 µm (Al) Kapton thickness is 25 µm. Bond wire connection between Al and Cu cable sections. Cable size is approximately 2.3 cm x 28 cm. Low mass region calculated X 0 for Al conductor = 0.073 % for Cu conductor = 0.232 % Preliminary Design: Hybrid Copper / Aluminum conductor flex cable Readout cable development Recent prototype (Cu conductor)

14. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 14 Michal Szelezniak Ladder prototype

15. Journées VLSI - FPGA - PCB de l'IN2P3, 5-7 June 2012 IPN Lyon 15 Michal Szelezniak Summary Production RDO board has been validated Production (2-nd gen) MTB board is currently in the design stage Good ladder performance with a limited number of decoupling capacitors Additional prototype ladders to be tested Installation of the prototype detector (3+ sectors) foreseen for late 2012 / early 2013