© 2008, Reinaldo Vega UC Berkeley Top-Down Nanowire and Nano- Beam MOSFETs Reinaldo Vega EE235 April 7, 2008

© 2008, Reinaldo Vega UC Berkeley References T. Ernst et al., “ Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO 2 /TiN gate stack, ” IEDM Tech. Dig., pp , L. K. Bera et al., “ Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs, ” IEDM Tech. Dig., pp , N. Singh et al., “ Ultra-Narrow Silicon Nanowire Gate-All- Around CMOS Devices: Impact of Diameter, Channel- Orientation and Low Temperature on Device Performance, ” IEDM Tech. Dig., pp , 2006.

© 2008, Reinaldo Vega UC Berkeley Motivation for Top-Down “ Conventional ” nanowire integration difficult due to random alignment. Also poor current density per layout area. Top-down patterning offers significant gains in nanowire placement control and current density. Key difficulty is patterning small nanowires …

© 2008, Reinaldo Vega UC Berkeley Multi-Layer Stacks Form Si/SiGe superlattice (epitaxial). Pattern a FinFET. Remove SiGe with CF 4 plasma (isotropic) etch. High pressure, low power. Selective (S ~ 60) etch to SiGe (20% Ge in this case). 3-D integrated nano-beams!!! Must avoid “ zipping ” (beam collapse). Inter-beam spacing and beam length constrained by zipping, which constrains beam count. Limitations further compounded by aspect ratio limitations for fin patterning (spacer or optical litho). Also consider Ge content  strain relaxation  defects  constrains SiGe thickness. W = 70 nm H = nm H/W ~3-3.5:1 L g = 0.7 um

© 2008, Reinaldo Vega UC Berkeley Multi-Layer Stacks by Oxidation Ge and Si oxidize at different rates. Serves several purposes: Selective lateral “ etch. ” Nanowire thinning. Ge pile-up in nanowire  higher drive current (maybe). Circumvent strain relaxation by using SiGe buffer layer between Si and Ge. Are these really nanowires? Or nano-beams? Or nano-fins? How does one define??? Different dimensionality for DOS. 50 nm 60 nm60 nm fins Dry O 2, 750C/60min Linear I ON scaling with #NW’s indicates zero SiGe enhancement. Needs > 16.6% Ge.

© 2008, Reinaldo Vega UC Berkeley Small Diameter Effects Coaxial gating reduces EOT  relaxed gate dielectric requirements. NW shape also plays a role. BUT … statistical Vt fluctuations. NW diameter variation affects Vt in many ways. Carrier confinement. EOT scaling. Body capacitance. Bandgap shift. Surface-to-volume ratio (interface states). NMOS PMOS

© 2008, Reinaldo Vega UC Berkeley Small Diameter Effects NMOS, PMOS Vt both increase (in magnitude) with NW diameter. Confinement, bandgap increase with NW scaling. I ON less sensitive to temperature with smaller NW diameter. Surface scattering dominated. Passivation is key here. Surface states also affect subthreshold swing. Non-ideal SS scaling with temperature. d nw = 6 nm L G = 350 nm