1. PHYSICS OF SEMICONDUCTOR DEVICES II
EE 221B:
PHYSICS OF SEMICONDUCTOR DEVICES II
More current topics
- Transport and Kinentics
Mobility, Vsat
Subthreshold Current Swing
Rs, Rd, Interface Transport
- Materials
Breakdown
Bandgap (Vbi)
Dopant Incorporation
- Electro-static coupling
SCE
-Quantum Effetcs
Tunneling
Cinv

2. SOI CMOS Low junction capacitance and leakage
Low power/High Speed Digital circuits
Perfect DC Isolation
Latch-up Free
High Density
Close to Ideal Substhreshold Swing (FD SOI)
Improved SCE
Small Body Effects

3. Advantage of SOI CMOS for Digital Circuits
Cascade V
S,2

13. So, What can we do?

14. Double Gate FETs

15. Tall FinFET - UCB

16. FinFET -- Trigate
TEMs of the PMOS channel under the gate (left) and in the
S/D region (right) showing the SiGe epitaxy in the S/D region.
C. Auth, et. A., 2012 VLSI Tech Symp.

17. NFET Performance
NMOS Ion-Ioff showing 13% Idsat improvement and 46% Ieff improvement relative to 32nm at 0.8V and 10nA. HP, MP and LP devices are benchmarked at 100nA, 10nA and 1nA Ioff respectively.
C. Auth, et. A., 2012 VLSI Tech Symp.

18. PFET Performance
PMOS Ion-Ioff showing 27% Idsat improvement and 40% Ieff
improvement relative to 32nm at 10nA and 0.8V.
C. Auth, et. A., 2012 VLSI Tech Symp.

19. Ideal Subthreshold Swing and Minimum SCE
Close to 60 mV/Decade I subthrehold swing for both nMOSFET and pMOSFET. Small VTH roll-off.
C. Auth, et. A., 2012 VLSI Tech Symp.

20. What about Ieff

21. Electron and hole mobility of group III-V compound semiconductors

23. Production SiGe pMOSFETs
Both electron and hole mobility on (110) SiGe surfaces are further enhanced in a <110> channel direction with appropriate uniaxial channel strain.

24. Production SiGe pMOSFETs
Excellent Mobilities

25. In0.53Ga0.47As n-MOSFET (Lg=450nm) with 50nm-thick LPCVD-grown SiN liner stressor and MOCVD-grown HfAlO gate dielectric & low resistance PdGe S/D contacts

26. InAs-OI MOSFETs
Takagi, 2012 VLSI Tech Symp

27. (a) ID-VG and (b) ID-VD characteristics of InAs-OI MOSFETs with a
Tbody of 3/3/3 nm, Tox = 6 nm.

28. Is III-V Channel for Real?
At constant IOFF = 10nA/µm
For strained Si, there is an increase in mobility (1.7x) and in saturation velocity (1.5x).
For ideal III-V, there is an increase in mobility (up to 8x) and in saturation velocity (up to 3x).
For realistic III-V channel, degradation in a) inversion charge density due to larger DS (dark space)
b) DIBL due to larger DS
c) subthreshold slope due to larger DS
d) DIBL due to larger dielectric constant
e) subthreshold slope due to larger dielectric constant
4. LP CMOS has degradation in performance whereas HP CMOS has improvement in performance compared to Si & strained-Si.
5. Therefore, the performance gain of III-V channel may be deteriorated compared to strained-Si.
1.7x mobility & 1.5x saturation velocity for strained-Si
Cumulative impact of constructive and destructive effects of III-V channels
6 Thomas Skotnicki & Frederic Boeuf, HOW CAN HIGH MOBILITY CHANNEL MATERIALS BOOST OR DEGRADE PERFORMANCE IN ADVANCED CMOS, Symposium on VLSI Technology Digest of Technical Papers, 2010.
7 M. Passlack et al., Classification and Benchmarking of III-V MOSFETs for CMOS, Symposium on VLSI Technology Digest of Technical Papers, 2010.

29. Evolution scenario for III-V/Ge devices on Si platform through heterogeneous integration

33. Summary Many Issues facing sub 20nm CMOS
Scaling Will End (run out of atoms)
But, before then
SCE
Transport Degradation
Parasitics
Need Innovative Device Architectures
If Planar scaling ends, why not go 3D?