Processor and Memory Organisation By: Prof. Mahendra B. Salunke Asst. Prof., Department of Computer Engg, SITS, Pune-41 URL: microsig.webs.com

Contents Structural unites in a processor Processor selection for an embedded system Memory devices Memory selection for an embedded system Direct memory access (DMA) Interfacing processor, memories and I/O devices

Structural units in a processor MAR: Memory Address Register MDR: Memory Data Register Internal bus Address bus Data bus Control bus BIU: Bus Interface Unit IR: Instruction Register ID: Instruction Decoder CU: Control Unit ARS: Application Register Set ALU: Arithmetic Logical Unit PC: Program Counter

Structural units in a high performance processors SRS: System Register Set SP: Stack Pointer IQ: Instruction Queue PFCU: Prefetch Control Unit I-Cache: Instruction cache BT-Cache: Branch Target Cache D-Cache: Data Cache MMU: Memory Management Unit FLPU: Floating Point Processing Unit FRS: Floating Point Register Unit Advanced Processing Units AOU: Atomic Operation Unit

Essential Characteristics to Consider during processor selection Instruction Cycle Time Internal Bus Width CISC or RISC PC bits and its reset value SP bits and its initial reset value Pipelined and Superscalar Units On-chip memories External Interrupts Interrupt Controller Bit manipulation Instructions Floating Point Processor DMA

Processor Specific Features Big-endian mode and little-endian mode Burst mode memory access Architecture: Harvard / Princeton I/O address space Atomic operations

Processor selection for an embedded system Processor instruction time Example Case 1~ 1µs with On-chip devices and memory Automatic Chocolate vending machine, robotic controller Case 2~ 10 to 40 ns with additional external memory 2 Mbps router, image processing, voice compression Case 3~ 5 to 10 nsMulti-port 100 Mbps Network Transceiver, Fast 100 Mbps switch Case 4< 1 nsVideo processor, mobile phone system

Memory devices ROM: –Masked ROM –EPROM –EEPROM –Flash Memory –PROM (OTP ROM) RAM: –SRAM –DRAM: EDO RAM, SDRAM, RDRAM, Parameterized Distributed RAM, Parameterized Block RAM

Memory selection for an embedded system Simple systems like automatic chocolate vending machine or robot needs no external memory The data acquisition system needs EEPROM or flash A mobile phone system needs 1MB plus RAM and 32kB plus EEPROM or flash device. Image / voice / video recording systems require a large flash memory So designer selects the processor and memory bases on system’s requirements.

Direct memory access (DMA) The DMA is required when a multi-byte data set or a block of data is to be transferred between two systems without the CPU intervention, except at the start and at the end. Modes of operations: –Single transfer –Burst transfer –Bulk transfer

Interfacing processor, memories and I/O devices An interfacing circuit consists of decoders and demultiplexers and is designed as per available control signal and timing diagrams of the bus signals. This circuit connects all the units, processor, memory devices and the IO devices. It is a part of the glue circuit used in the system and is in a GAL or FPGA.

Interfacing memory devices and ports in 8051

Interfacing memory devices and ports in 68HC11

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