1. Computer operation is of how the different parts of a computer system work together to perform a task.

2. Central Processing Unit The central processing unit (CPU) is the brain of a computer system. All processing is carried out by the CPU. Input Unit Data are input through the input unit. An input device puts the data into a form that is acceptable to the computer. Main Memory The Main memory stores the programs and data to be processed by the CPU. It also holds the processed information before it is output. Output Unit The results are output by the output unit. An output device outputs results in a form that can be understood by humans. Secondary Storage As the main memory is temporary and of limited capacity, some data and programs are stored in the backing store for future use. Communication Unit The communication unit connects a computer system to other computers so that data and programs can be sent to and received from them. All devices connected to the system unit are called peripherals. Flow of data The components of a Computer System System Unit

3. Registers Both the ALU and Control Unit contain high-speed temporary storage locations called registers. They hold program instructions and data temporary during processing. Central Processing Unit (CPU) The CPU consists of Arithmetic and Logic Unit (ALU) Control Unit. (see next slide for their functions)

4. Arithmetic and Logical Unit (ALU) The ALU performs arithmetic and logical operations (AND, OR, NOT, =, >, <, … ). It contains a register called Accumulator that temporarily holds results of ALU operations. Control Unit (CU) The control unit retrieves repetitively an instruction from the main memory and stores it temporarily in a register called Instruction Register (IR). It then interprets (decodes) the instruction in IR and sends out control signals to other parts of the computer to carry out the instruction. By means of a register called Program Counter (PC), the Control Unit is able to keep track of the sequence of instructions that are to be processed. PC contains the address of the memory location storing the next instruction to be executed and will be automatically increased to point to that location when an instruction is fetched.

5. CalculatingCircuitry PC (Program Counter) IR (Instruction Register) [5]  Acc Acc (Accumulator) 18 [6] +[Acc]  Acc CU (Control Unit) ALU (Arithmetic and Logic Unit) CPU (Central Processing Unit) InstructionDecoder

6. Main memory is divided into memory locations. Each location has a memory address. By specifying its memory address, a memory location can be identified. 0123456701234567 0101101010010101 0111101001010101 1011010010001101 1100001001000101 1001010000101010 0000010100010100 1100001010000110 0010000100000110 0010111100000110 A memory location holding a piece of data or an instruction. The address for this location is 1. Memory addresses Note: Memory addresses are in binary. Decimal numbers are used here for simplicity. Main Memory

7. CalculatingCircuitry 0 1 2 3 4 5 6 7 PC (Program Counter) IR (Instruction Register) [5]  Acc Acc (Accumulator) 18 [6] +[Acc]  Acc CU (Control Unit) ALU (Arithmetic and Logic Unit) CPU (Central Processing Unit) Main Memory InstructionDecoder

8. Machine Instructions Machine instructions are in binary. Symbolic forms are used here to tell the meanings of the instructions used. InstructionAction [5]  Acc load the contents of location 5 to the Accumulator [6]+[Acc]  Acc Add the contents of location 6 and the Accumulator leaving the result in the Accumulator [Acc]  7 Store the contents of the Accumulator to location 7 Note: [x] means the content of x Here are the instructions for adding two numbers:

9. The example in the next slide shows how a program is executed in a computer. Note the following: 1.The program and data to be processed are stored in the main memory. 2. The instructions are fetched to and decoded by the CU one by one repetitively. 3. The CU sends out control signals to instruct other parts to carry out the instruction.

10. CalculatingCircuitry 0 [5]  Acc 1 [6]+[Acc]  Acc 2 [Acc]  7 3Stop 4 5 18 6 26 7 PC (Program Counter) IR (Instruction Register) 0 [5]  Acc Acc (Accumulator) 18 + 18 44 1 [6] +[Acc]  Acc 26 2 [Acc]  7 CU (Control Unit) ALU (Arithmetic and Logic Unit) CPU (Central Processing Unit) Main Memory InstructionDecoder 44 Stop 3

11. Machine Cycle The process that a CPU executes an instruction is referred as a machine cycle. The machine cycle is repeated each time the computer executes an instruction. Store the result Execute the instruction Decode the instruction Fetch an instruction

12. How memory works

13. 000 001 010 011 100 101 110 111 0 1 1 0 1 1 0 1 In the following, each memory location holds 8 bits of data. Each memory location can store a number of bits of data and has a memory address. The memory location with memory address 010 holds the data 01101101. How memory works Note that a memory address is not a piece of data stored. It corresponds to an electronic signal generated by the address decoder. (next slide)

14. 000 001 011 100 101 110 111 0 1 1 0 1 1 0 1 Address Decoder 010010 Address Bus A memory address is not a piece of data stored. It corresponds to an electronic signal generated by the address decoder. Data Bus 010........ 0 1 1 0 1 1 0 1

15. How address decoder works - decoder.swf

16. Memory size is limited by the number of bits to store an address (related to computer architecture) 10 bit address => 2 10 = 1K memory locations 0 1023 10 bit address Address decoder Memory

17. Cache memory

18. Cache Memory Cache memory is high speed memory (RAM) that a processor uses to hold recently used instructions or data temporarily. In case these instructions and data are needed again, the processor can get them directly from the cache memory rather than going back to the much slower main memory. Computers spend a lot of time in loops, repeating the same sequence of instructions, so using cache memory can greatly improve performance. Reference reading: cache.doc

19. L1 (Level 1) Cache: located on the CPU chip - faster - more expensive - smaller capacity L2 (Level 2) Cache: on nearby chips with high-speed link to the CPU - slower than L1 cache - less expensive - larger capacity

21. Cache of a CPU, main memory and others Demo: Use CPU-Z to view

22. System Bus

23. Each bus is a shared transmission medium, so that only one device can transmit along a bus at any one time. Data and control signals travel in both directions (bi-directional) between the processor, memory and I/O controllers. Addresses travel only one way (uni-directional) along the address bus: the processor sends the address of an instruction, or of data to be stored or retrieved, to memory or to an I/O controller.

24. The control bus is a bi-directional bus (two-way). The control lines of the bus send control signals from CU to other system components to control and co-ordinate execution of operations. Interrupt requests are sent from other system components to the CU. The data and address buses are shared by all components of the system. Control lines ensure that access to and use of the data and address buses by different components of the system does not lead to conflict. The purpose of the control bus is to transmit command, timing and specific status information between system components. Timing signals indicate the validity of data and address information. Command signals specify operations to be performed. Specific status signals indicate the state of a data transfer request, or the status of a request by a component to gain control of the system bus. Refer to Reference Notes – System Bus for more.

25. I/O controllers Peripheral devices cannot be connected directly to the processor. Each peripheral operates in a different way and it would not be sensible to design processors to directly control every possible peripheral. The processor controls and communicates with a peripheral device through an I/O or device controller. http://www.mitchellwebdesign.com/arm/lecture1/lecture1-3-2.html An animation showing how control lines, address and data buses and the system clock work together to complete a task:

26. DRAM (Dynamic RAM) need to be continuously re-charged to maintain the memory => slower, more heat generated, cheaper SRAM (Static RAM) no need to be re-charged to maintain the memory => faster, less heat generated, more expensive SDRAM -- synchronous dynamic RAM

27. EPROM, or erasable programmable read only memory, is a type of memory chip that retains its data when its power supply is switched off. An EPROM can be erased by exposing it to strong ultraviolet light from a mercury-vapor light source. EEPROM is user-modifiable read-only memory (ROM) that can be erased and reprogrammed (written to) repeatedly through the application of higher than normal electrical voltage generated externally or internally in the case of modern EEPROMs. Flash memory such as Flash USB memory, SD memory cards are examples of EEPROM.

28. Instruction pipelining