1. Pyxis Aaron Martin April Lewis Steve Sherk

2. September 5, 2005 Pyxis16002 General-purpose 16-bit RISC microprocessor 16 16-bit registers 24-bit address bus Up to 16MB of addressable memory

3. September 5, 2005 Pyxis16003 Registers 16 registers 3 special purpose –$r0 – zero –$r14 – stack pointer –$r15 – return address 13 general purpose –$r1 - $r13 Status register (sr) –8 bits – carry (c), overflow (o), negative (n), zero (z), interrupt enable (i), less than (l), 2 bits unused Program counter (pc) Accumulator high (ah) and accumulator low (al) –Used for multiply and divide Page register (pr) –Sets the high order 8 bits in the 24-bit address space

4. September 5, 2005 Pyxis16004 Instruction Formats 16-bit instructions 7-bit opcode 1 bit to indicate information in next word rd is source and target rs is source Branch instructions use special format opcoderdrs Displacement / Immediate ext 0 015 3 4789 opcodebranch typeaddress 089121315 R-type B-type

5. September 5, 2005 Pyxis16005 Instruction Set

6. September 5, 2005 Pyxis16006 Instruction Set

7. September 5, 2005 Pyxis16007 Addressing Modes Register direct Register indirect plus displacement –Use r0 for absolute addressing PC-relative Immediate

8. September 5, 2005 Pyxis16008 Interrupts Options for handling interrupts –Handled by hardware Each interface wired to its own pin –Handled by software Use interrupt vector that points to different routines Have separate priority level for each interface All interrupts go to same routine that polls each device to see which one caused the interrupt

9. September 5, 2005 Pyxis16009 Block Diagram Major Components PC Instruction Register Registers Control ALU Memory Instruction [15:8] Instruction [7:4] Instruction [3:0] Read / Write Register Read Register OpCodeDest. RegSource Reg 1587430

10. September 5, 2005 Pyxis160010 Sub-systems Internal to the microprocessor –Fetch and Memory access logic addressing modes –ALU add, sub, mult, div, memory access calculations (PC+offset) –Control logic micro instructions, control signal labels –Register implementation External –Serial bus implementation hardware associated with serial port

11. September 5, 2005 Pyxis160011 Assembler Converts assembly code into machine language Uses a look-up table to find machine code for each instruction –Some instruction are “psudo-instructions” implemented with other, lower level instructions Written in Perl and implemented on a PC –Perl is good for parsing and string manipulation Machine code saved on EPROM and loaded onto microprocessor –.asm .HEX  EPROM burning software

12. September 5, 2005 Pyxis160012 Hardware XCV300 FPGA  - 322,970 logic gates  - 8 KB on-chip RAM 128KB off-chip SRAM 128KB off- chip EPROM

13. September 5, 2005 Pyxis160013 Input / Output Devices Serial RS232 port Monitor / LCD Keyboard / Keypad USB port

14. September 5, 2005 Pyxis160014 Feature Priority General-purpose processor –Multi-cycle design –Complete reduced instruction set –Some test code, Game, or Benchmark Program Assembler On-chip hardware divider C compiler Floating-point unit L1 data and instruction cache 5 stage pipeline design

15. September 5, 2005 Pyxis160015 Roles and Responsibilities Aaron –Logic design –Verilog programming April –Assembler –Software interfaces Steve –Hardware components –Hardware interfaces All –Integration and Test –Documentation

16. September 5, 2005 Pyxis160016 Schedule

17. September 5, 2005 Pyxis160017 Risks and Contingency Plan RiskResolution Problems in logic designOptional features will not be implemented Bad PartsSeveral XCV300 chips are available, other components are inexpensive Problems with hardware interfaces Several options exist (I.e. LCD vs. monitor, RS232 vs. USB) Problems with software interfaces Validate all software interfaces early in schedule to allow time to correct if necessary

18. Questions