1. INTV1 & MMCV4 By: Prof. Mahendra B. Salunke Asst. Prof., Department of Computer Engg., SITS, Pune-41 Email: msalunke@gmail.com URL: microsig.webs.com

2. Contents INTV1 MMCV4

3. INTV1 Block Diagram

4. Features Provides two to 122 I-bit maskable interrupt vectors (0xFF00–0xFFF2) Provides one X-bit maskable interrupt vector (0xFFF4) Provides a non-maskable software interrupt (SWI) or background debug mode request vector (0xFFF6) Provides a non-maskable unimplemented opcode trap (TRAP) vector (0xFFF8) Provides three system reset vectors (0xFFFA–0xFFFE) (reset, CMR, and COP) Determines the appropriate vector and drives it onto the address bus at the appropriate time Signals the CPU that interrupts are pending

5. Features Continued… Provides control registers which allow testing of interrupts Provides additional input signals which prevents requests for servicing I and X interrupts Wakes the system from stop or wait mode when an appropriate interrupt occurs or whenever XIRQ is active, even if XIRQ is masked Provides asynchronous path for all I and X interrupts, (0xFF00–0xFFF4) (Optional) selects and stores the highest priority I interrupt based on the value written into the HPRIO register

6. Modes of Operations Normal operation Special operation Emulation modes Low power modes

7. External Signals Most interfacing with the interrupt sub- block is done within the core. However, the interrupt does receive direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and XIRQ pin data.

8. Memory Map

9. Register Definition: ITCR

10. Register Definition: ITEST

11. Register Definition: HPRIO

12. Functional Description The interrupt sub-block processes all exception requests made by the CPU. These exceptions include interrupt vector requests and reset vector requests.

13. Low-Power Modes Operation in Run Mode Operation in Wait Mode Operation in Stop Mode

14. Resets INT supports three system reset exception request types: –normal system reset or power-on-reset request, –crystal monitor reset request, and –COP watchdog reset request. The type of reset exception request must be decoded by the system and the proper request made to the core. The INT will then provide the service routine address for the type of reset requested.

15. Interrupts The INT contains a register block to provide interrupt status and control, an optional highest priority I interrupt (HPRIO) block, and a priority decoder to evaluate whether pending interrupts are valid and assess their priority.

16. Exception Priority

17. Memory Mapping Control Block (MMCV4)

18. Features Registers for mapping of address space for on-chip RAM, EEPROM, and FLASH (or ROM) memory blocks and associated registers Memory mapping control and selection based upon address decode and system operating mode Core address bus control Core data bus control and multiplexing Core security state decoding

19. Features Emulation chip select signal generation (ECS) External chip select signal generation (XCS) Internal memory expansion External stretch and ROM mapping control functions via the MISC register Reserved registers for test purposes Configurable system memory options defined at integration of core into the system-on-a-chip (SoC).

20. Block Diagram

21. Functional Description The MMC sub-block performs four basic functions of the core operation: –bus control, –address decoding and select signal generation, –memory expansion, and –security decoding for the system.

22. Bus Control The MMC controls the address bus and data buses that interface the core with the rest of the system. This includes the multiplexing of the input data buses to the core onto the main CPU read data bus and control of data flow from the CPU to the output address and data buses of the core. In addition, the MMC manages all CPU read data bus swapping operations.

23. Address Decoding Select Priority and Mode Considerations Emulation Chip Select Signal External Chip Select Signal

24. Memory Expansion The HCS12 core architecture limits the physical address space available to 64K bytes. The program page index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF in the physical memory space.

25. Module Memory Map Address Offset RegisterAccess 0x0010Initialization of Internal RAM Position Register (INITRM) R/W 0x0011Initialization of Internal Registers Position Register (INITRG) R/W 0x0012Initialization of Internal EEPROM Position Register (INITEE) R/W 0x0013Miscellaneous System Control Register (MISC)R/W 0x0014Reserved-- 0x0017Reserved-- 0x001CMemory Size Register 0 (MEMSIZ0)R 0x001DMemory Size Register 1 (MEMSIZ1)R 0x0030Program Page Index Register (PPAGE)R/W 0x0031Reserved--

26. Contact Details: Email: msalunke@gmail.com URL: microsig.webs.com