Main Project : Simple Processor Mini-Project : 3-bit binary counter (using 7400 series) Memory By Oluwayomi B. Adamo.

Slides:

Advertisements

Similar presentations

VHDL Lecture 1 Megan Peck EECS 443 Spring 08.

Advertisements

Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.

28/10/2007DSD,USIT,GGSIPU1 Latch & Register Inference.

Arbitrary Waveform Discussion 5.5 Example 34.

1 VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi.

Ring Counter Discussion D5.3 Example 32. Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i)

Generic Multiplexers: Parameters Discussion D2.5 Example 8.

Logic Design Fundamentals - 3 Discussion D3.2. Logic Design Fundamentals - 3 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.

Registers VHDL Tutorial R. E. Haskell and D. M. Hanna T2: Sequential Logic Circuits.

Integer Square Root.

6/27/20061 Sequence Detectors Lecture Notes – Lab 5 Sequence detection is the act of recognizing a predefined series of inputs A sequence detector is a.

6/12/20151 Sequence Detectors Lecture Notes – Lab 4 Sequence detection is the act of recognizing a predefined series of inputs A sequence detector is a.

Single-Cycle Instructions VHDL Tutorial R. E. Haskell and D. M. Hanna T5: VHDL ROM.

FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.

Counters Discussion D5.3 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

Finite State Machines Discussion D7.1 Mealy and Moore Machines.

Multiplication Discussion Multiplier Binary Multiplication 4 x 4 Multiplier.

CSCI 660 EEGN-CSCI 660 Introduction to VLSI Design Lecture 3 Khurram Kazi Some of the slides were taken from K Gaj ’ s lecture slides from GMU ’ s VHDL.

VHDL And Synthesis Review. VHDL In Detail Things that we will look at: –Port and Types –Arithmetic Operators –Design styles for Synthesis.

Finite State Machines Discussion D8.1 Example 36.

Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s.

Registers Lab 5 Mano and Kime Sections 5-2, 5-3, 5-7.

CSCI 641 – EENG CSCI-641/EENG-641 Computer Architecture Khurram Kazi.

Shift Registers Discussion D5.2 Example Bit Shift Register qs(3) qs(2) qs(1) qs(0) if rising_edge(CLK) then for i in 0 to 2 loop s(i) := s(i+1);

4-bit Shift Register. 2-bit Register Serial-in-serial-out Shift Register.

1 Part V: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

Designing with FPGAs ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.

George Mason University ECE 545 – Introduction to VHDL Memories: RAM, ROM Advanced Testbenches ECE 545 Lecture 9.

VHDL in 1h Martin Schöberl. AK: JVMHWVHDL2 VHDL /= C, Java,… Think in hardware All constructs run concurrent Different from software programming Forget.

ENG241 Digital Design Week #8 Registers and Counters.

George Mason University ECE 545 – Introduction to VHDL Variables, Functions, Memory, File I/O ECE 545 Lecture 7.

Copyright(c) 1996 W. B. Ligon III1 Getting Started with VHDL VHDL code is composed of a number of entities Entities describe the interface of the component.

2’s Complement 4-Bit Saturator Discussion D2.8 Lab 2.

Introduction to Computer Design n Memory n Review of simple processor and memory n Fetch and execute cycle n Processor organization n Executing instructions.

Feb. 26, 2001Systems Architecture I1 Systems Architecture I (CS ) Lecture 12: State Elements, Registers, and Memory * Jeremy R. Johnson Mon. Feb.

1 RAM. 2 PS2_Keyboard: entity work.Keyboard generic map (AddressBits => ADDRESSLENGTH) port map (Reset => Reset, Clock => ClockVGA, PS2Clock => PS2Clock,

George Mason University ECE 448 – FPGA and ASIC Design with VHDL ECE 448 Lecture 10 Memories: RAM, ROM.

 Seattle Pacific University EE Logic System DesignCounters-1 Shift Registers DQ clk DQ DQ ShiftIn Q3Q3 Q2Q2 DQ Q1Q1 Q0Q0 A shift register shifts.

1 Part III: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal.

Data Storage VHDL ET062G & ET063G Lecture 4 Najeem Lawal 2012.

CEC 220 Digital Circuit Design VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Slide 1 of 13.

Controllers ENGIN 341 – Advanced Digital Design University of Massachusetts Boston Department of Engineering Dr. Filip Cuckov.

Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal.

July 2, 2001Systems Architecture I1 Systems Architecture II (CS 282) Lab 3: State Elements, Registers, and Memory * Jeremy R. Johnson Monday July 2, 2001.

Figure 9.1 Architecture of a Simple Computer System.

George Mason University Behavioral Modeling of Sequential-Circuit Building Blocks ECE 545 Lecture 8.

Lecture 11 Xilinx FPGA Memories Part 2

Registers and Counters Discussion D8.1. Logic Design Fundamentals - 3 Registers Counters Shift Registers.

CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #19 –VHDL.

Sequential statements (1) process

Main Project : Simple Processor Mini-Project : Vending Machine Memory

Lecture L5.1 Mealy and Moore Machines

Registers and Counters

Part III: SYSTEM DESIGN

Hardware Description Languages

Part IV: VHDL CODING.

Field Programmable Gate Array

مدار های ترکیبی دیکدر لامپ های هفت قسمتی یکی از دیکدر هایی که اغلب به کار برده می شود،دیکدر 4 به 7 برای تبدیل کد bcd به کد هفت بیتی برای لامپ های seven.

ECE 545 Lecture 17 RAM.

A Greatest Common Divisor (GCD) Processor

Fibonacci Sequence Lecture L4.1 Lab 3.

Modeling of Circuits with a Regular Structure

Fast, Asynchronous SRAM

Variables variable variable_name: variable_type

Modeling of Circuits with Regular Structure

디 지 털 시 스 템 설 계 UP2 Kit를 이용한 카운터 설계

(Sequential-Circuit Building Blocks)

Presentation transcript:

Main Project : Simple Processor Mini-Project : 3-bit binary counter (using 7400 series) Memory By Oluwayomi B. Adamo

Simple Processor

Design Specification Memory Register Programming Counter Instruction Register ALU Control Unit Input Output

Memory

Memory(VHDL) ENTITY ram IS GENERIC ( bits: INTEGER := 8; -- # of bits per word words: INTEGER := 16); -- # of words in the -- memory PORT ( wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 TO words-1; data_in: IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0); data_out: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0)); END ram; ARCHITECTURE ram OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR (bits-1 DOWNTO 0); SIGNAL memory: vector_array; BEGIN PROCESS (clk, wr_ena) BEGIN IF (wr_ena='1') THEN IF (clk'EVENT AND clk='1') THEN memory(addr) <= data_in; END IF;

Memory contd. END IF; END PROCESS; data_out <= memory(addr); END ram;

Register(VHDL) entity reg is port(clk, ld, rst : in std_logic; Data: in std_logic_vector( 2 downto 0); Q: out std_logic_vector( 2 downto 0)); end reg; architecture behv of reg is signal Q_tmp: std_logic_vector( 2 downto 0); begin process(clk, ld, rst, data) begin if (rst = '0' )then Q_tmp '0'); elsif (clk='1' and clk'event) then if (ld = '1' )then Q_tmp <= Data; end if; end process; Q <= Q_tmp; end behv;