1. Fast, Asynchronous SRAM
Discussion D8.2

7. buff3.vhd en input output library IEEE; use IEEE.STD_LOGIC_1164.all;
entity buff3 is
generic (width:positive);
port(
input : in STD_LOGIC_vector(width-1 downto 0);
en : in STD_LOGIC;
output : out STD_LOGIC_vector(width-1 downto 0) );
end buff3;
architecture buff3 of buff3 is
begin
output <= input when en = '1' else (others => 'Z');
input
output

8. RAM Module

9. RAM1

10. library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity clock_pulse2 is
port (
inp, cclk, clr: in std_logic;
outp1: out std_logic;
outp2: out std_logic );
end clock_pulse2;

11. architecture clock_pulse2_arch of clock_pulse2 is
signal delay1, delay2, delay3, delay4: std_logic;
begin
process(cclk, clr)
if clr = '1' then
delay1 <= '0';
delay2 <= '0';
delay3 <= '0';
delay4 <= '0';
elsif cclk'event and cclk='1' then
delay1 <= inp;
delay2 <= delay1;
delay3 <= delay2;
delay4 <= delay3;
end if;
end process;
outp1 <= delay1 and delay2 and (not delay3);
outp2 <= delay1 and delay2 and delay3 and (not delay4);
end clock_pulse2_arch;

12. Counter clock
Address WE
BTN2

13. library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity ram1 is
port(
mclk : in STD_LOGIC;
BTN3 : in STD_LOGIC;
BTN2 : in STD_LOGIC;
BTN0 : in STD_LOGIC;
SW : in STD_LOGIC_VECTOR(7 downto 0);
AN : out STD_LOGIC_VECTOR(3 downto 0);
AtoG : out STD_LOGIC_VECTOR(6 downto 0);
LD : out STD_LOGIC_VECTOR(7 downto 0);
A : out STD_LOGIC_VECTOR(17 downto 0);
dp : out STD_LOGIC;
LB1 : out STD_LOGIC;
UB1 : out STD_LOGIC;
CE1 : out STD_LOGIC;
OE : out STD_LOGIC;
WE : out STD_LOGIC;
IO10 : inout STD_LOGIC_VECTOR(15 downto 0) );
end ram1;

14. begin
dp <= '1';
clr <= BTN3;
OE <= oen;
IO10(7 downto 0) <= IOdata;
IO10(15 downto 8) <= "ZZZZZZZZ";
A <= qout;
LD <= qout(7 downto 0);
WE <= outp1 nand BTN2;
oen <= BTN2;
UB1 <= '1';
LB1 <= '0';
CE1 <= '0';
ground <= " ";
load <= not BTN2;

15. U0: clock_pulse2 port map
(inp => BTN0, cclk => cclk, clr => clr, outp1 => outp1, outp2 => outp2);
U1: count18 port map
(clk => outp2, clr => clr, q => qout);
U2: x7segb port map
(x(15 downto 8) => ground, x(7 downto 0) => xin, clr => clr, cclk => cclk, AN => AN, AtoG => AtoG);
U3: buff3 generic map(width => bus_width) port map
(input =>SW, en => oen, output => IOdata);
INreg: reg generic map(width => bus_width) port map
(d => IOdata, load => load, clr => clr, clk =>outp2,
q => xin);
end ram1;