Introduction to Programmable Logic Devices John Coughlan STFC Technology Department Detector & Electronics Division

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Programmable Logic is a Key Underlying Technology for PP Experiments. n First-Level and High-Level Triggering n Data Transport (Networks) n Computers interacting with Hardware (Networks) n Silicon Trackers (Millions of Data Channels) Commercial Devices. Developments driven by Industry. Telecomms, Gaming, Aerospace, Automotive, Set-top boxes…. PPD Lectures

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( CMS CERN LHC Particle Physics Electronics Custom Electronics Chips ASICs ANALOGUE $$$ Rad Hard, Low Power

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( CMS CERN LHC Electronics Rooms Particle Physics Electronics Trigger Systems. DAQ Systems. DIGITAL Custom Electronics Chips ASICs ANALOGUE $$$ Rad Hard, Low Power Custom Digital Processing Boards VME Bus Crates

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Particle Physics Electronics n Special Dedicated Logic Functions (not possible in CPUs) u Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate Timing u Massively Parallel Data Processing (Silicon Trackers with Millions of Channels) Custom Designed Printed Circuit Boards PCBs. Commercial Programmable Logic Devices, FPGAs

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( CMS DAQ/Trigger Architectures CMS “Telecoms Network” ~ 1 Tbps Fully custom PP ASICs CPUs Commodity PCs Programmable Logic DIGITAL

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Lecture Outline n Programmable Logic Devices u Basics u Evolution n FPGA Field Programmable Gate Array u Architecture n Design Flow u Hardware Description Languages u Design Tools

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Digital Logic Logic Gates

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Digital Logic Logic Gates Transistor Switches

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Digital Logic Logic Gates Transistor Switches < 40 nm ! $$$ MOORE’S LAW

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Digital Logic Black Box SUM of PRODUCTS Truth Table (Look Up Table LUT) Digital Logic Function 3 Inputs Product AND (&) Sum OR (|)

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Digital Logic Black Box SUM of PRODUCTS Truth Table (Look Up Table LUT) Digital Logic Function 3 Inputs Product AND (&) Sum OR (|)

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Digital Logic Black Box SUM of PRODUCTS Truth Table (Look Up Table LUT) Digital Logic Function 3 Inputs Product AND (&) Sum OR (|)

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Programmable Logic Devices PLDs Un-programmed State n SUM of PRODUCTS n (Re-)Programmble Links n Reconfigurable n GLUE LOGIC Logic Functions Planes of ANDs, ORs Inputs Outputs ANDs ORs

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Programmable Logic Devices PLDs Un-programmed State n SUM of PRODUCTS n (Re-)Programmble Links n Reconfigurable n GLUE LOGIC Logic Functions Planes of ANDs, ORs Inputs Outputs ANDs ORs

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Programmable Logic Devices PLDs Un-programmed State n SUM of PRODUCTS n (Re-)Programmble Links n Reconfigurable n GLUE LOGIC Logic Functions Planes of ANDs, ORs Inputs Outputs ANDs ORs

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Programmable Logic Devices PLDs Un-programmed State n SUM of PRODUCTS n (Re-)Programmble Links n Reconfigurable n GLUE LOGIC Logic Functions Programmed PLD Product Terms Sums Planes of ANDs, ORs Inputs Outputs ANDs ORs

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Programmable Logic Devices PLDs Logic Functions Programmed PLD Product Terms Sums

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Programmable Logic Devices PLDs Logic Functions Programmed PLD Product Terms Sums x x x x x

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Programmable Logic Devices PLDs Logic Functions Programmed PLD Product Terms Sums x x x x x x x n GLUE LOGIC

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Complex PLDs n CPLDs n Programmable PLD Blocks n Programmable Interconnects n Electrically Erasable links CPLD Architecture Feedback Outputs

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Sequential Circuits n Combinational Logic (Larger circuits difficult to predict) n Synchronous Logic driven by a CLOCK n Registers, Flip Flops (Memory) Inputs

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Sequential Circuits Register CLOCK New Output every clock edge n Combinational Logic (Larger circuits difficult to predict) n Synchronous Logic driven by a CLOCK n Registers, Flip Flops (Memory) Inputs Intermediate EDGES

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Sequential Circuits Register CLOCK New Output every clock edge Shift Registers, Pipelines, Finite State Machines … n Combinational Logic (Larger circuits difficult to predict) n Synchronous Logic driven by a CLOCK n Registers, Flip Flops (Memory) Clock Rate determines speed Comb Logic Must meet Timing => Predictable circuits Inputs Intermediate EDGES

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Field Programmable Gate Arrays FPGA n Field Programmable Gate Array u ‘Simple’ Programmable Logic Blocks u Massive Fabric of Programmable Interconnects u Standard CMOS Integrated Circuit fabrication process as for memory chips (Moore’s Law)

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Field Programmable Gate Arrays FPGA n Field Programmable Gate Array u ‘Simple’ Programmable Logic Blocks u Massive Fabric of Programmable Interconnects u Standard CMOS Integrated Circuit fabrication process as for SRAM memory chips (Moore’s Law) Huge Density of Logic Block ‘Islands’ 1,000 … 100,000’s in a ‘Sea’ of Interconnects FPGA Architecture

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Field Programmable Gate Arrays FPGA

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Logic Blocks n Logic Functions implemented in Look Up Table LUTs. n Flip-Flops. Registers. Clocked Storage elements. n Multiplexers (select 1 of N inputs) FPGA Fabric Logic Block

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Look Up Tables LUTs n LUT contains Memory Cells to implement small logic functions n Each cell holds ‘0’ or ‘1’. n Programmed with outputs of Truth Table n Inputs select content of one of the cells as output 3 Inputs LUT -> 8 Memory Cells Static Random Access Memory SRAM cells 3 – 6 Inputs Multiplexer MUX

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Look Up Tables LUTs n LUT contains Memory Cells to implement small logic functions n Each cell holds ‘0’ or ‘1’. n Programmed with outputs of Truth Table n Inputs select content of one of the cells as output n Configured by re-programmable SRAM memory cells 3 Inputs LUT -> 8 Memory Cells Static Random Access Memory SRAM cells 3 – 6 Inputs Multiplexer MUX

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Logic Blocks n Larger Logic Functions built up by connecting many Logic Blocks together

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Logic Blocks n Larger Logic Functions built up by connecting many Logic Blocks together n Determined by SRAM cells SRAM cells

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Clocked Logic n Registers on outputs. CLOCKED storage elements. n Synchronous FPGA Logic Design, Pipelined Logic. n FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency) FPGA Fabric Clock from Outside world (eg LHC bunch frequency) Special Routing for Clocks

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Input Output I/O Getting data in and out Up to > 1,000 I/O “pins” (several 100 MHz)

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Input Output I/O Getting data in and out Up to > 1,000 I/O “pins” (several 100 MHz) Special I/O SERIALISERS ~ 10 Gbps transfer rates Optical TRx

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Designing Logic with FPGAs n Design Capture. n High level Description of Logic Design. u Graphical descriptions u Hardware Description Language (Textual)

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Hardware Description Languages n Language describing hardware (Engineers call it FIRMWARE) n Doesn’t behave like “normal” programming language ‘C/C++’ n Describe Logic as collection of Processes operating in Parallel n Language Constructs for Synchronous Logic n Compiler (Synthesis) Tools recognise certain code constructs and generates appropriate logic n Not all constructs can be implemented in FPGA! n 2 Popular languages are VHDL, VERILOG n Easy to start learning… Hard to master!

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( VHDL ENTITY Declaration Input Output to Module (STD LOGIC) SIGNALS Declaration WIRES CONCURRENT ASSIGNMENTS CONDITIONAL ASSIGNMENTS => MULTIPLEXERS

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( VHDL COMPONENT Declaration PROCESS Declaration. CONCURRENT functions. Synchronous Logic.

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Designing Logic with FPGAs n High level Description of Logic Design u Hardware Description Language (Textual) n Compile (Synthesis) into NETLIST. n Boolean Logic Gates. n Target FPGA Device u Mapping u Routing n Bit File for FPGA n Commercial CAE Tools (Complex & Expensive) n Logic Simulation Design Flow

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Designing Logic with FPGAs n High level Description of Logic Design u Hardware Description Language (Textual) n Compile (Synthesis) into NETLIST. n Boolean Logic Gates. n Target FPGA Device u Mapping u Routing n Bit File for FPGA n Commercial CAE Tools (Complex & Expensive) n Logic Simulation Design Flow

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Designing Logic with FPGAs n High level Description of Logic Design u Hardware Description Language (Textual) n Compile (Synthesis) into NETLIST. n Boolean Logic Gates. n Target FPGA Device u Mapping u Routing n Bit File for FPGA n Commercial CAE Tools (Complex & Expensive) n Logic Simulation Design Flow

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Configuring an FPGA n Millions of SRAM cells holding LUTs and Interconnect Routing n Volatile Memory. Lose configuration when board power is turned off. n Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card n Configuration takes ~ secs JTAG Port

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Configuring an FPGA n Millions of SRAM cells holding LUTs and Interconnect Routing n Volatile Memory. Lose configuration when board power is turned off. n Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card n Configuration takes ~ secs JTAG Testing JTAG Port Programming Bit File

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Field Programmable Gate Arrays FPGA n Large Complex Functions n Re-Programmability, Flexibility. n Massively Parallel Architecture n Processing many channels simultaneously cf MicroProcessor n Fast Turnaround Designs n Standard IC Manufacturing Processes. Moore’s Law n Mass produced. Inexpensive. n Many variants. Sizes. Features. n PP Not Radiation Hard  n Power Hungry  n No Analogue 

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( FPGA Trends n State of Art is 40nm on 300 mm wafers n Top of range >500,000 Logic Blocks n >1,000 pins (Fine Pitched BGA) n Logic Block cost ~ 1$ in 1990 n Today < 0.1 cent n Problems u Power. Leakage currents. u Design Gap F CAE Tools

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Summary n Programmable Logic Devices u Basics u Evolution n FPGA Field Programmable Gate Arrays u Architecture n Design Flow u Hardware Description Languages u Design Tools Importance for Particle Physics Experiments

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( References n The Design Warrior’s Guide to FPGAs u Clive Maxfield, Newnes Elsevier n VHDL for Logic Synthesis u Andrew Rushden, Wiley n FPGA manufacturer web sites u u n FPGA Online u u u

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Spare Slides

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( System on a Chip n Add Embedded Micro-Processor Cores in Fabric u e.g. RISC PowerPC u Ethernet Interface n Run Operating System e.g. Linux n Combine Micro-Processor & Massively Parallel Logic n Dual Design Flows u Firmware HDL u Software C

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Time line of Programmable devices

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Application Specific Integrated Circuits ASICs Large Complex Functions. Millions of Gates Customised for Extremes of Speed, Low Power, Radiation Hardness (Very) Expensive to Design (in small quantities) > $1 Million mask set (Very) Hard to Design. Long Design cycles. NOT Reprogrammable. FROZEN in Silicon. High Risk Limited Complexity Thousands of Gates Cheap Easy to Design Reprogrammable. Custom Fabricated Design from Scratch Prefabricated Programmed