ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Firmware - Matt Warren1 Physics & Astronomy HEP Electronics Matthew Warren John Lane, Martin Postranecky TIM Firmware ATLAS SCT TIM FDR/PRR 28 June 2004

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Firmware - Matt Warren2 General Firmware written in VHDL –Maintainable. –Support by almost all hardware. –Used by other collaborators. Tools: –Mentor Graphics FPGA Advantage 5.4 –Xilinx ISE 5.2i Firmware structured in blocks similar to the old PLD sub-divisions. Synchronous design principles followed.

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Firmware - Matt Warren3 FPGA/Code Structure FPGA1 is the ‘Manager’ –VME Interface –Controls access to local bus –Manages resets –Can re-configure FPGA2’s PROM –Provides status information on FPGA2 etc. FPGA2 is the ‘TIM Function’ –Front Panel Signals –J3 Backplane Signals –Sequencer RAM, ID FIFO’s are internal

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Firmware - Matt Warren4 TIM-3 Functional Layout FPGA1 VME Interface & Board Manager Address Bus Config EEPROM FPGA2 Back-Plane Signals Front-Panel Signals TTCrx VME Control Data Bus Base Addr. Preset Switches fpga2_reset spare_bus Debug Mode Select Switch 16 Clocks & Clk Control vme_read vme_select Trigger Window Board ID 8 8 Front-Panel LEDs Internal Trig, FER, ECR vme_write 44 clk JTAG FP and PO Resets ROD Busy 16 Config EEPROM FPGA1 Addr(31:1) Data(31:0) Debug Header 16 ROD Busy LEDs 16 Debug LEDs Debug Header 16 Debug LEDs fpga2_ok 88 jtagx_en FPGA2 TIM Function VME I/O MRMW v

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Firmware - Matt Warren5 TIM Hardware for Firmware JTAG programmable PROMs used (Xilinx 18V) –FPGAs use Master Serial Mode for loading Lower VME Address Bus (15:1) on both FPGAs –Allows local address decoding Entire VME data-bus available to both FPGAs. –32 bit registers if needed Debug Hardware (see next slide)

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Firmware - Matt Warren6 Debug/Expansion Features 16 line dedicated spare lines between FPGAs. 16 line dedicated debug lines per FPGA –Connected to header – logic-analyser access –8 debug lines/FPGA connected to SMD LEDs Mode/Debug hex-switch connected to both FPGAs –minor changes in operation without downloading new code (e.g. LEDs map). ROD Busy LEDs on front-panel available to code. PCB version ID readable by FPGAs Enough resources to add extra functions –e.g. Fixed Frequency Veto (more later)

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Firmware - Matt Warren7 FPGA Resource Utilisation From Xilinx ISE Place & Route Report: FPGA1 –Number of External GCLKIOBs 1 out of 4 25% –Number of External IOBs 161 out of % –Number of BLOCKRAMs 4 out of 14 28% –Number of SLICEs 280 out of % –Number of DLLs 1 out of 4 25% –Number of GCLKs 1 out of 4 25% –Number of TBUFs 128 out of % FPGA2 –Number of External GCLKIOBs 2 out of 4 50% –Number of External IOBs 244 out of % –Number of BLOCKRAMs 64 out of 72 88% –Number of SLICEs 1843 out of % –Number of DLLs 1 out of 4 25% –Number of GCLKs 1 out of 4 25% –Number of TBUFs 160 out of %

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Firmware - Matt Warren8 Outstanding code I2C interface to TTCrx –Works on TIM-2, so low priority System for re-configuring FPGA2 from software –Firmware very ‘dumb’ – software will do the work. Finalise Fixed Frequency Trigger Veto System –No big changes – just need iterate over best style of operation with community.

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Firmware - Matt Warren9 Simulation Components Simulated using ModelSim Most simulation fast enough to be carried out on the whole FPGA level The VME interface was tested across both FPGAs including models of the external bus-transceivers. Simulations are controlled via the bus interface. Procedures have were written to do bus-like reads/writes. These allowed routines similar to those in the test software to be used.