1. Digital Atlas Vme Electronics - DAVE - Module
Poster Number 126
Topical Workshop on Electronics for Particle Physics ( TWEPP-2011 ) Vienna, Austria to 30 Sept. 2011
UNIVERSITY OF
CAMBRIDGE
Cavendish Laboratory, Department of Physics, University of Cambridge Maurice GOODRICK Richard Shaw
Dave Robinson
Department of Physics and Astronomy, University College London Martin Postranecky Matthew Warren
Red LED –FPGA Prog.
Xilinx PROM
Prog. FPGA Switch
GSI 18x4Mb SRAM
Ext. 5V/3A Conn.
Spartan3E FPGA
Clock MUX/PLL
VME Base Address A<31-28> A<27-24>
7x Supply Monitor
Red LED x Supply OK
MHz XTAL Osc.
VME J2
Clk+4 Delay Lines
VME J1
Blue LED x Supply OK
Set Serial No.
SER<7-4>
SER<3-0>
SIL JTAG for FPGA
USB Reset Switch
IN<7-0> TTL/NIM Sel.
Set Mod. Record
MR<7-4>
MR<3-0>
CLK-IN<1-0> ECL/NIM Sel.
CLK-OUT<1-0> ECL/NIM Sel.
OUT<7-0> TTL/NIM Sel.
DEBUG & DownloadUSB MCU
40-pin DIL HEADER
DAVE Module
ATLAS-SCT has developed a new ATLAS trigger card, 'Digital
Atlas Vme Electronics' ( "DAVE" ) standalone as experienced in
combined runs.
The unit was designed to provide a versatile array of interface
and logic resources, including a large FPGA
Interfaces to both VME bus and USB hosts
Originally planned as replacement for ATLAS-SCT stand-alone
trigger & veto logic NIM module
Decision to incorporate many more generic features
Adopted all ATLAS CTP functions to exactly duplicate ATLAS
running condition
Random trigger, simple and complex deadtime, ECR, BCR, etc. are being generated to give exactly the same conditions in
standalone running as experienced in combined runs
DAVE card thus evolved into a powerful and flexible logic
module
Potentially useful to all ATLAS subsystems as well as for other
non-ATLAS users
Firmware is developed in a modular fashion allowing code
contributions from interested users
Initially the core SCT requirements ( vetoing trigger generation
around a BCR ) will be implemented
Further development will aim to provide other CTP functionality, with random trigger generator up to 100kHz, simple and complex dead-time, busy gating, ECR, BCR, etc. generation
USB MCU JTAG
Ext. +5V / 3A Power Conn.
CLK-IN<1-0> 2x LEMOs 00
Global Reset Switch ( FPGA, MCU )
4-pin USB
AUX. DIL 16x I/Os
FPGA JTAG
Prog. MODE Hex Switch.
3x STATUS LEDs ( Programmable )
3x4 LEDs ( Programm. )
Programm. Reset Switch
CLK-OUT<1-0> 2x LEMOs 00
DATA-IN<7-0> 8x LEMOs 00
DATA-OUT<7-0> 8x LEMOs 00
40-pin DIL HEADER
VME J1
VME J2