University of Tehran 1 Interface Design Memory Modules Omid Fatemi

University of Tehran 2 Outline Memory variations The memory cell

University of Tehran 3 Processor Timing Diagram for any memory read machine cycle

University of Tehran 4 Processor Timing Diagram for any memory write machine cycle

University of Tehran 5 Memory Terms Capacity –Kbit, Mbit, Gbit Organization –Address lines –Data lines Speed / Timing –Access time Write ability –ROM –RAM

University of Tehran 6 ROM Variations Mask Rom PROM – OTP EPROM – UV_EPROM EEPROM Flash memory

University of Tehran 7 RAM Variations SRAM DRAM NV-RAM –SRAM – CMOS –Internal lithium battery –Control circuitry to monitor Vcc

University of Tehran 8 Memories in General Computers have mostly RAM ROM (or equivalent) needed to boot ROM is in same class as Programmable Logic Devices (PLDs), in which are also FPGAs –Lots of memories in these devices

University of Tehran 9 Simple View of RAM Of some word size n Some capacity 2 k k bits of address line Maybe have read line Have a write line Have a CS (chip select)

University of Tehran 10 1K x 16 memory Variety of sizes –From 1-bit wide Issue is no. of pins Memory size specified in bytes –This would be 2KB memory 10 address lines and 16 data lines

University of Tehran 11 Writing Sequence of steps –Setup address lines –Setup data lines –Activate write line (maybe a pos edge) –Usually latch on the next edge

University of Tehran 12 Reading Steps –Setup address lines –Activate read line –Data available after specified amt of time

University of Tehran 13 Chip Select Usually a line to enable the chip

University of Tehran 14 Writing

University of Tehran 15 Reading

University of Tehran 16 Minimum Mode

University of Tehran 17 Minimum Mode When Memory is selected?

University of Tehran 18 Minimum Mode 2 20 bytes or 1MB

University of Tehran 19 What are the memory locations of a 1MB (2 20 bytes) Memory? A19 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA FFFFF1111 Example: 34FD

University of Tehran 20 Interfacing a 1MB Memory to the 8088 Microprocessor

University of Tehran 21 Instead of Interfacing 1MB, what will happen if you interface a 512KB Memory?

University of Tehran 22 What are the memory locations of a 512KB (2 19 bytes) Memory? A18 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA FFFF

University of Tehran 23 Interfacing a 512KB Memory to the 8088 Microprocessor What do we do with A19?

University of Tehran 24 What if you want to read physical address A0023?

University of Tehran 25 What if you want to read physical address A0023? A19 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA 3210 A A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”, the memory cannot “see” this.

University of Tehran 26 What if you want to read physical address 20023? A18 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA For memory it is the same as previous one.

University of Tehran 27 Interfacing two 512KB Memory to the 8088 Microprocessor

University of Tehran 28 Interfacing two 512KB Memory to the 8088 Microprocessor Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read. Solution: Use address line A19 as an “arbiter”. If A19 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.

University of Tehran 29 Interfacing two 512KB Memory to the 8088 Microprocessor : RD WR CS

University of Tehran 30 What are the memory locations of two consecutive 512KB (2 19 bytes) Memory? A19 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA FFFF FFFFF1111

University of Tehran 31 Interfacing two 512KB Memory to the 8088 Microprocessor When the  P outputs an address between to FFFFF, this memory is selected When the  P outputs an address between to 7FFFF, this memory is selected

University of Tehran 32 Interfacing two 512KB Memory to the 8088 Microprocessor

University of Tehran 33 Interfacing two 512KB Memory to the 8088 Microprocessor

University of Tehran 34 What if we remove the lower memory?

University of Tehran 35 What if we remove the lower memory? When the  P outputs an address between to FFFFF, this memory is selected When the  P outputs an address between to 7FFFF, no memory chip is selected !

University of Tehran 36 Full and Partial Decoding Full Decoding –When all of the “useful” address lines are connected the memory/device to perform selection Partial Decoding –When some of the “useful” address lines are connected the memory/device to perform selection –Using this type of decoding results into roll-over addresses

University of Tehran 37 Full Decoding

University of Tehran 38 Full Decoding A19 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA FFFFF1111 A19 should be a logic “1” for the memory chip to be enabled

University of Tehran 39 Full Decoding A19 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA FFFF Therefore if the microprocessor outputs an address between to 7FFFF, whose A19 is a logic “0”, the memory chip will not be selected

University of Tehran 40 Partial Decoding

University of Tehran 41 Partial Decoding A19 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA FFFF FFFFF1111 The value of A19 is INSIGNIFICANT to the memory chip, therefore A19 has no bearing whether the memory chip will be enabled or not

University of Tehran 42 Partial Decoding A19 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA FFFF FFFFF1111 ACTUAL ADDRESS

University of Tehran 43 Partial Decoding A19 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA FFFF FFFFF1111 ACTUAL ADDRESS

University of Tehran 44 Interfacing two 512K Memory Chips to the 8088 Microprocessor

University of Tehran 45 Interfacing one 512K Memory Chips to the 8088 Microprocessor

University of Tehran 46 Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 2)

University of Tehran 47 Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 3)

University of Tehran 48 Interfacing four 256K Memory Chips to the 8088 Microprocessor

University of Tehran 49 Interfacing four 256K Memory Chips to the 8088 Microprocessor

University of Tehran 50 Interfacing four 256K Memory Chips to the 8088 Microprocessor

University of Tehran 51 Interfacing four 256K Memory Chips to the 8088 Microprocessor

University of Tehran 52 Interfacing several 8K Memory Chips to the 8088  P

University of Tehran 53 Interfacing 128 8K Memory Chips to the 8088  P

University of Tehran 54 Interfacing 128 8K Memory Chips to the 8088  P

University of Tehran 55 Memory chip#__ is mapped to: A19 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA

University of Tehran 56 Memory Chip 8K SRAM to be specific: –8Kx8 bits SRAM

University of Tehran Block Diagram

University of Tehran Function Table

University of Tehran 59 Memory Chip 8K EPROM to be specific: –8Kx8 bits EPROM

University of Tehran Block Diagram Chip enable Output enable

University of Tehran 61 Operating Modes

University of Tehran 62 Programming 2764 after each erasure for UV-EPROM): –all bits of the M2764A are in the “1" state. The only way to change a “0" to a ”1" is by ultraviolet light erasure. Programming mode when: –VPP input is at 12.5V –E and P are at TTL low. The data to the data output pins. The levels required for the address and data inputs are TTL.

University of Tehran 63 Interfacing 128 8K Memory Chips to the 8088  P

University of Tehran 64 When interfacing memory chips to a microprocessor, consider the following: TAVDV – address access time TRLDV – read access time TDVWH – memory setup time TWHDX – data hold time TWLWH – write pulse width Refer to 8088 data manual8088 data manual

University of Tehran 65 HM6264B Series Read Timing Diagram t AA, t OE

University of Tehran 66 HM6264B Series Write Timing Diagram t DW, t DH, t WP

University of Tehran 67 Timing Requirements for 6264 SRAM TAVDV = t AA TRLDV = t OE TDVWH = t DW TWHDX = t DH TWLWH = t WP

University of Tehran 68 HM6264B Series Read TIMING REQUIREMENTS

University of Tehran 69 HM6264B Series Write TIMING REQUIREMENTS

University of Tehran 70 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and HM6264B-8L

University of Tehran 71 Timing Requirements for HM6264B-8L TAVDV = t AA = 85 ns TRLDV = t OE = 45 ns TDVWH = t DW = 40 ns TWHDX = t DH = 0 ns TWLWH = t WP = 55 ns

University of Tehran 72 Can we interface a 2764 to the 8088 chip which uses a 4MHz clock?

University of Tehran 73 M2764A Read Mode AC Characteristics

University of Tehran 74 M2764A Read Mode Timing Diagram

University of Tehran 75 Timing Requirements for 2764 EPROM TAVDV = t AVQV TRLDV = t GLQV TDVWH = N/A TWHDX = N/A TWLWH = N/A

University of Tehran 76 Timing Requirements for 2764 EPROM TAVDV = t AVQV = ? TRLDV = t GLQV = ? TDVWH = N/A TWHDX = N/A TWLWH = N/A

University of Tehran 77 M2764A Read Mode AC Characteristics

University of Tehran 78 Timing Requirements for M2764A-3 TAVDV = t AVQV = 180 ns TRLDV = t GLQV = 65 ns TDVWH = N/A TWHDX = N/A TWLWH = N/A

University of Tehran 79 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and M2764A-3

University of Tehran 80 What if we need to interface a “slow” memory to the 8088?

University of Tehran 81 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and a certain “slow” memory chip

University of Tehran 82

University of Tehran 83 Recall:Write Pulse Width / Write-Time (TWLWH)

University of Tehran 84 Write Pulse Width / Write-Time (TWLWH) w/ 1 wait state

University of Tehran 85 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and a certain memory chip caused by 1 wait state during a memory write on the “slow” memory chip

University of Tehran 86 How do we produce a wait state? By turning the READY input of the 8088 microprocessor to LOW

University of Tehran 87

University of Tehran 88 Requirements for the READY input of the ns (min)

University of Tehran 89 Requirements for the RDY of the 8284

University of Tehran 90 Memory - Global Organisation

University of Tehran 91 Static vs Dynamic RAM SRAM vs DRAM DRAM stores charge in capacitor –Disappears over short period of time –Must be refreshed SRAM easier to use –Faster –More expensive per bit –Smaller sizes

University of Tehran 92 Structure of SRAM Control logic One memory cell per bit –Cell consists of one or more transistors –Not really a latch made of logic Logic equivalent

University of Tehran 93 Static RAM Cell

University of Tehran 94 Bit Slice Cells connected to form 1 bit position Word select gates one latch from address lines Note it selects Reads also B (and B not) set by R/W, Data In and BitSelect

University of Tehran 95 Bit Slice can Become Module Basically bit slice is a X1 memory

University of Tehran X 1 RAM What is this?

University of Tehran 97 Tri-State Have three states: H, L, and Hi-Z –High impedance –Behaves line no output connection if in Hi-Z state –Allows connecting multiple outputs

University of Tehran 98 Multiplexed with Hi-Z Normal behavior is blue area Smoke

University of Tehran 99 Row/Column If RAM gets large, there is a large decoder Also run into chip layout issues Larger memories usually “2D” in a matrix layout

University of Tehran X 1 as 4 X 4 Array Two decoders –Row –Column Address just broken up Not visible from outside

University of Tehran 101 Change to 8 X 2 RAM Minor change in logic Also pinouts Address 011 (for example)

University of Tehran 102 Memory - Internal Organisation

University of Tehran 103 Realistic Sizes Imagine 256K memory as 32K X 8 One column layout would need 15-bit decoder with 32K outputs! Can make a square layout with 9-bit row and 6-bit column decoders

University of Tehran 104 SRAM Performance Current ones have cycle times in low nanoseconds (say 2.5ns) Used as cache (typically offchip secondary cache) Sizes up to 8Mbit or so for fast chips SRAMs: –Asynchronous –Synchronous

University of Tehran 105 Micron SRAMs SyncBurst ZBT QDR DDR (common IO) DDR (separate IO) Synchronous Control inputs are captured at clock edges

University of Tehran 106 SRAM Categories SYNCBURST –Internal 2-bit burst counter –Appropriate for cache line size of four –Two bus master support (CPU and cache controller) –ADV# controls number of words –Not suited for more frequent bus turnaround applications ZBT (Zero Bus Turnaround) –Internal 2-bit burst counter –FLOW-Through ZBT »One clock cycle delay »Less data latency and less frequency –Pipelined ZBT »While data is delivered the memory array is free for the next data access »Higher frequency

University of Tehran 107 Pentium Cache System

University of Tehran 108 SRAM QDR QDR (Quad Data Rate) –Low latency, higher frequency (network applications) –Less ASIC pin count –Separate read and write busses  simultaneous read and write –Clock pair (K,K#)

University of Tehran 109 SRAM DDR DDR (common IO) –In cases like 16 read then 16 write QDR is half wasted –Common IO busses for input and output DDR (separate IO) –Hybrid of DDR and QDR