1. ENG241 Digital Design
Week #11
Memory Systems
School of Engineering

2. Week #11 Topics Random Access Memory Comparison Larger Wider Memories
Static RAM
Array of RAM ICs
Dynamic RAM
Types of Dynamic RAM
Comparison
Larger Wider Memories
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3. Resources Chapter #9, Mano Sections 9.1 Memory Definitions
9.2 Random Access Memory
9.3 SRAM Integrated Circuits
9.4 Array of SRAM ICs
9.5 DRAM ICs
9.6 DRAM Types
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4. A Digital Computer System
Data/Instructions/code
clock
Inputs: Keyboard, mouse, modem, microphone
Outputs: CRT, LCD, modem, speakers
Answer: Part of specification for a PC is in MHz. What does that imply? A clock which defines the discrete times for update of state for a synchronous system. Not all of the computer may be synchronous, however.
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5. Picture of Memory
You can think of memory as being one big array of data.
The address serves as an array index.
Each address refers to one word of data.
You can read or modify the data at any given memory address, just like you can read or modify the contents of an array at any given index.
Word

6. Memory Signal Types Memory signals fall into three groups
Address bus - selects one of memory locations
Data bus
Read: the selected location’s stored data is put on the data bus
Write (RAM): The data on the data bus is stored into the selected location
Control signals - specifies what the memory is to do
Control signals are usually active low
Most common signals are:
CS: Chip Select; must be active to do anything
OE: Output Enable; active to read data
WR: Write; active to write data

7. Properties of Memory
Volatile: Memory contents disappears if power turned off
Typical computer RAM
PDA, Smart Phone, iPADs, …
Nonvolatile: Contents of memory remain even if power turned off
ROM
PROM, EEPROM
Flash memories
Magnetic memories like disk, tape

8. Memories in General Computers have two types of memory Volatile Memory
RAM (Random Access Memory)
Static RAM usually used for Cache
Dynamic RAM used for Main Memory
Non-Volatile Memory
ROM (Read Only Memory), FLASH
Used to store permanent programs in a computer system (booting)

9. Classification of Memory

10. Key Design Metrics

11. Memory Hierarchy
The design constraints on a computer memory can be summed up by three questions (i) How Much (ii) How Fast (iii) How expensive.
There is a tradeoff among the three key characteristics
A variety of technologies are used to implement memory system
Dilemma facing designer is clear  large capacity, fast, low cost!!
Solution  Employ memory hierarchy
Flip Flops
Cost
registers
Static RAM
Cache
Capacity
Dynamic RAM
Main Memory
Access
Time
Disk Cache
Magnetic Disk
Removable Media

12. Main Memory vs. Cache
Dynamic RAM
Static RAM
Registers
Static RAM

13. Memory Registers Static RAM Dynamic RAM Bus CPU Cache Controller
PCI
DRAM
EISA/PCI Bridge
Hard Drive
Video
Adaptor
PC Card 1
PC Card 2
SCSI
PC Card 3
Local CPU / Memory Bus
Peripheral Component Interconnect Bus
EISA PC Bus
Bus
Co-processor
Dynamic RAM

14. RAM vs. ROM ROM RAM Read only Read/write Non-Volatile Volatile Slower
Variants
PROM,EPROM
EEPROM, FLASH
Application
Programs
Constants
Codes, e.t.c
RAM
Read/write
Volatile
Faster access time
Variants
SRAM
DRAM
Application
Variables
Dynamic memory allocation
Heaps, stacks

15. Random Access Memories
So called because it takes the same amount of time to address any particular part
Types of RAM
Static RAM (SRAM), fast, expensive
Dynamic RAM (DRAM), slow, cheap
How is memory accessed?
Address Lines, Data Lines
Control Signals (R/W, chip select, …)

16. Simple View of RAM Of some word size n=4,8,16 …. Some capacity 2k
k bits of address line, k=10,11,..
Has a read line
Has a write line

17. 1K x 16 memory Variety of sizes From 1-bit wide Issue is no. of pins
Memory size specified in bytes
1K x 16 bit  2KB memory
10 address lines and 16 data lines

18. Chip Select and R/W Lines
R/W Lines enable reading/writing
Usually a chip select line is used.
Why?
To enable RAM chip to be accessed.

19. Memory: Writing Sequence of steps
Setup address lines
Setup data lines
Activate write line (maybe a pos edge)
The write cycle time is the maximum time from the application of the address to the completion of all internal memory operations required to store a word.

20. Writing: Timing Waveforms
CPU operates at 50 MHz (20 ns)
4 clock cycles to perform a write

21. Memory Reading Steps Read cycle usually is shorter than write cycle.
Setup address lines
Activate read line
Data available after specified amount of time
Read cycle usually is shorter than write cycle.

22. Memory Waveform: Reading
CPU operates at 50 MHz (20 ns)
65 ns required for a read cycle

23. Static RAM: 4T and 6T

24. Static RAM: Internal Structure

25. Simplify Modeling using Latch
Storage is modeled by an SR latch.
Control logic
One memory cell per bit
For select = 0, the stored content is held.
For select = 1, the stored content is determined by values on B and B’
The outputs are gated by the select line also.

26. Bit Slice Cells connected to form 1 bit position
Word Select gates one latch from address lines
Note it selects Reads also
B (and B’) set by R/W, Data In and BitSelect
When R/W = 0 and BitSelect = 1, then if Data in = 1  the latch will be set (i.e. a 1 is written)

27. Bit Slice can Become Module
Basically bit slice is a one Dimensional array of memory
What type of hardware do we need to access one row at a time?

28. 16 X 1 RAM 4 address lines required to access 16 locations.
A Decoder is added to select the different words (each 1 bit wide).
For 16 words we need a 4-to-16 line Decoder

29. Row/Column Practical memories contains thousands of words!!
If RAM gets large, there is a huge decoder
Also run into chip layout issues
How can we change the structure of Memory to solve this problem?
Rearrange the memory into “2D” i.e., matrix layout

30. 16 X 1 as 4 X 4 Array Two decoders Address just broken up
Row
Column
Address just broken up
Not visible from outside

31. 16 X 1 as 4 X 4 Array
Employing 2 decoders instead of 1 row decoder is called coincident selection
Row Select and Column Select
A3A2A1A0=0000 will attempt to choose RAM cell 0.

32. Change from 16x1 to 8 X 2 RAM Minor change in logic
Try addressing 011 on board
Cells 6,7 are chosen for reading or writing.

33. A Single Row Decoder Imagine 32k x 8 = 256K bit memory
15 address lines are required (for 32K)
One column layout would need 15-bit decoder with 32,768 outputs
For a single decoder that would mean 32,800 gates
This is not practical!
How about coincident selection?

34. Coincident Selection A 32K X 8 contains 256 Kbits
A 15 bit address line is required.
To make the number of rows and columns equal we take the square root of 256K, giving 512 = 29
A 9-to-512 decoder is required for the rows (9 address lines are fed to the Row Decoder).
Remember we need 8 bits of output!! (Column Decoder?)
For the columns 512/8 = 64 = 26
A 6-to-64 line decoder is required for the columns (6 address lines are fed to the Column Decoder).
Total number of gates is = 576 (i.e. reducing the total gate count by more than 50!)

35. SRAM Performance
Current SRAMs have cycle times in low nanoseconds (say 2.5ns)
Used as cache (typically on-chip or off-chip secondary cache)
Sizes up to 256 Mbit or so for fast chips

36. Larger/Wider Memories
Made up from sets of chips
Consider a 64K by 8 RAM
Note new symbols for sets of lines, 8 & 16 bits wide

37. Larger: 256k x 8 Connect all output data lines together (tristate)
Connect all input data line together
16 lines of address to fetch a word in any DRAM chip
How to select the specific RAM chip?

38. Larger Capacity Decoder for high-order 2 bits Selects chip
Look at selection logic
Address ranges

39. Wider Memory – 64K X 16

40. Dynamic memory Dynamic memory is built with capacitors.
A stored charge on the capacitor represents a logical 1.
No charge represents a logic 0.
However, capacitors lose their charge after a few milliseconds. The memory requires constant refreshing to recharge the capacitors. (That’s what’s “dynamic” about it.)
Dynamic RAMs tend to be physically smaller than static RAMs.
A single bit of data can be stored with just one capacitor and one transistor, while static RAM cells typically require 4-6 transistors.
This means dynamic RAM is cheaper and denser—more bits can be stored in the same physical area.

41. Dynamic RAM Capacitor can hold charge Transistor acts as gate
No charge is a 0
Can close switch & add charge to store a 1
Then open switch (disconnect)

42. DRAM Cell

43. DRAM read operations Precharge bit line to VDD/2.
Take the word line HIGH.
Detect whether current flows into or out of the cell.
Note: cell contents are destroyed by the read!
Must write the bit value back after reading.

44. DRAM write operations Take the word line HIGH.
Set the bit line LOW or HIGH to store 0 or 1.
Take the word line LOW.
Note: The stored charge for a 1 will eventually leak off.

45. Dynamic RAM (… continued)
Select
Stored 1
Stored 0
To Pump T B C
DRAM cell
(a)
(b)
(c)
Write 1
Write 0
(d)
(e)
Read 1
Read 0
Warning: (d), (e), (f), and (g) are animated. Each animation is triggered with a mouse click
and goes through two steps at 1 second intervals.
(f)
(g)
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46. DRAM Characteristics (Why Slow!)
Destructive Read
When cell read, charge removed
Charge must be restored after a read
Refresh
Capacitors are not perfect! there’s steady leakage
Charge must be restored periodically
DRAM are dense (lots of cells) so there are many address lines.
To reduce the physical size of DRAM we can reduce the number of pins by applying the address lines serially in two parts:
Row Address, and then
Column Address

47. How DRAM Works
A7A6A5A4
A3A2A1A0
A7A6A5A4A3A2A1A0

48. DRAM-chip internal organization
64K x 1 DRAM

49. DRAM charge leakage
Typical devices require each cell to be refreshed once every 4 to 64 mS.

50. DRAM Logic Diagram

51. Delay until data available
DRAM Read Signaling
DRAM has a lower pin count by using same pins for row and column addresses
Delay until data available

52. DRAM Write Timing

53. DRAM Refresh Many strategies Logic on chip
Refresh counter and Refresh controller
Refresh counter is used to provide the address of the row of DRAM cell to be refreshed.

54. CAS Before RAS Set column address Apply CAS first (opposite of RW)
Then toggle RAS enough times to cycle through row addresses
On-board refresh counter applies the row addresses
CAS
RAS
Col Add
Row Add
Row Add
Row Add
Row Add

55. DRAM Chip Types DRAM - Dynamic RAM FPM RAM - Fast page-mode RAM
EDO RAM - Extended Data Out RAM
BEDO RAM - Burst Extended-data-out RAM
SDRAM - Synchronous Dynamic RAM
DDRRAM Double Data Rate RAM

56. Page Mode DRAM DRAMs made to read & write blocks Example
Assert RAS, leave asserted
Assert CAS multiple times to read sequence of data
Similar for writes 56

57. Synchronous DRAM (SDRAM)
Double Data Rate SDRAM
Transfers data on both edges of the clock 57

58. DRAM Evolution
There has been multiple improvements to the DRAM design in the past 20 years.
SDRAM: A clock signal was added making the design synchronous.
DDR SDRAM: The data bus transfers data on both rising and falling edge of the clock.
DDR2 SDRAM: Second generation of DDR memory scales to higher clock frequencies.
DDR3 SDRAM: Third generation has lower power consumption, higher clock frequency and denser modules
DDR4 SDRAM: Fourth generation, improvement over DDR3, high bandwidth, higher speed. However it is not compatible with any earlier type of (RAM) due to different signaling voltages. 58

59. DDR SDRAM Comparison

60. Memory Technologies DRAM: Dynamic Random Access Memory
upside: very dense (1 transistor per bit) and inexpensive
downside: requires refresh and often not the fastest access times
often used for main memories
SRAM: Static Random Access Memory
upside: fast and no refresh required
downside: not so dense and not so cheap
often used for caches

61. Summary RAMs with different characteristics Static RAM Dynamic RAM
For different purposes
Static RAM
Simple to use, small, expensive
Fast, used for cache
Dynamic RAM
Complex to interface, largest, cheap
Needs periodic refresh
Dense, slow, used in Main Memory

62. Links Ram Guides (not very technical)

63. End Slides